Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

UCOMISS is the quiet version of COMISS: it compares the low singles of two operands and sets ZF, PF and CF the same way (all three for an unordered result), but raises the invalid-operation exception only when an input is a signaling NaN. A quiet NaN, which is what arithmetic produces from an invalid operation, passes through without a trace. It is the compare that compiled code shows most:

  • Clang 23 at -O2 uses it for every float comparison in C, < and > included, and GCC 14 for == and !=, for isless(), isgreater() and the other quiet macros, and for isunordered().
  • isnan(x) becomes ucomiss xmm0, xmm0 and SETP in both compilers, since only a NaN is unordered with itself.
  • The six _mm_ucomi*_ss intrinsics compile to it, with the parity test that keeps an equality false for a NaN.

COMISS explains how the flags map to condition codes and why compilers swap the operands for “less than”.

What the recorded cases show

On Zen 5, a quiet NaN compared with another quiet NaN set ZF, PF and CF and left MXCSR unchanged, while a signaling NaN set MXCSR.IE in a VUCOMISS case. A denormal input sets the denormal flag, DE, even though nothing is computed from it: comparing the smallest normal single with a negative denormal gave “greater” and set DE. With MXCSR.DAZ set, denormal inputs count as zeros of the same sign instead.

UCOMISS writes no XMM register, and its memory operand is four bytes at any alignment. VUCOMISS is the VEX and EVEX form (the EVEX one can suppress all exceptions with {sae}), UCOMISD the version for doubles, and AVX10.2’s VUCOMXSS the quiet partner of VCOMXSS.

Forms

Every encoding of UCOMISS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
UCOMISS xmm, m32 UCOMISS_XMMss_MEMssNP 0F 2E /rSSE
UCOMISS xmm, xmm UCOMISS_XMMss_XMMssNP 0F 2E /rSSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low singles of the two sources are compared, and the result sets ZF, PF and CF.
UCOMISS: the low element to the flagsThe flags come from single 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.0123xmm1aZFPFCFRFLAGS0123xmm2or m32b

The flags come from single 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = ucomi(xmm1.f32[0], src2.f32[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# only an SNaN raises IE

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
UCOMISS xmm, xmm/m32
xmmexplicitread
xmm/m32explicitread
RFLAGSimplicitwrite

Flags

M modified, 0 cleared; blank: not affected. How to read.
OFSFZFAFPFCF
All forms
00M0MM

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms
follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to UCOMISS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_ucomieq_ss int _mm_ucomieq_ss(__m128 __a, __m128 __b)

UCOMISS xmm, xmm Legacy -msse

_mm_ucomige_ss int _mm_ucomige_ss(__m128 __a, __m128 __b)

UCOMISS xmm, xmm Legacy -msse

_mm_ucomigt_ss int _mm_ucomigt_ss(__m128 __a, __m128 __b)

UCOMISS xmm, xmm Legacy -msse

_mm_ucomile_ss int _mm_ucomile_ss(__m128 __a, __m128 __b)

UCOMISS xmm, xmm Legacy -msse

_mm_ucomilt_ss int _mm_ucomilt_ss(__m128 __a, __m128 __b)

UCOMISS xmm, xmm Legacy -msse

_mm_ucomineq_ss int _mm_ucomineq_ss(__m128 __a, __m128 __b)

UCOMISS xmm, xmm Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE

SSE
CPUID.01H:EDX[25] SSE

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-735 (UCOMISS)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  6. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.