Instruction
UD0
Raises an invalid-opcode exception (#UD); some processors decode it without the ModR/M byte and operands that others read.
- Extensions
- Forms
- 3 (3 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
UD0
UD0 | 0F FF | Base instruction set |
UD0 r32, m32
UD0_GPR32_MEMd | 0F FF /r | Base instruction set |
UD0 r32, r32
UD0_GPR32_GPR32 | 0F FF /r | Base instruction set |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
PPRO_UD0_SHORT | No CPUID bit: part of the base instruction set. | Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Granite Rapids, Diamond Rapids, Bonnell, Saltwell, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Sierra Forest, Clearwater Forest |
PPRO_UD0_LONG | No CPUID bit: part of the base instruction set. | NetBurst (Prescott, Nocona), Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2 |
More General-purpose instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.