UNPCKHPD instruction (SSE2)

UNPCKHPD pairs the high doubles of its two operands: the first operand’s high double moves down to element 0 and the second’s goes above it, so _mm_unpackhi_pd(a, b) gives a[1] and b[1]. The low doubles are ignored. UNPCKLPD, the low-half twin, describes the family and its legacy traits, which apply here too: the memory form reads 16 aligned bytes and uses only the upper eight, and the result keeps bits 128 and up of the register (see SSE and AVX). VUNPCKHPD does the same in each 128-bit lane of a wider register.

Zen 5’s recorded unpckhpd xmm4, xmmword ptr [mem] moved the high double of XMM4 to the low half and put bytes 8 to 15 of memory above it, and unpckhpd xmm4, xmm4 copied the high double into both halves.

Moving the high double down

That register form brings element 1 down to where scalar instructions see it, and SSE2 code uses it for horizontal work. In our builds at -O2, for the default target and with -march=x86-64-v2, GCC 14 and Clang 23 compile v[0] + v[1] on a __m128d to UNPCKHPD and ADDSD, GCC with unpckhpd xmm0, xmm0 after saving a copy, Clang unpacking a copy. Clang uses it on floats too: for _mm_movehl_ps(v, v) in a sum of four singles, it emits UNPCKHPD where GCC keeps MOVHLPS, the same 64 bits moved either way.

With two different registers it transposes pairs. Clang splits an array of complex doubles into real and imaginary arrays with two whole-vector loads, MOVLHPS for the real parts and UNPCKHPD for the imaginary ones, and the reverse loop, building the complex array, uses the same two. GCC keeps the split scalar and builds the complex array with MOVSD and MOVHPD loads.

Forms

Every encoding of UNPCKHPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`UNPCKHPD xmm, m128` UNPCKHPD_XMMpd_MEMdq	`66 0F 15 /r`	SSE2
`UNPCKHPD xmm, xmm` UNPCKHPD_XMMpd_XMMq	`66 0F 15 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the high doubles of both sources alternate in the result, those of xmm1 in the even places.

Result doubles 1 to 0: b1, a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(2):
    j = i // 2 + 1
    if i % 2 == 0:
        xmm1.q[i] = src1.q[j]
    else:
        xmm1.q[i] = src2.q[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`UNPCKHPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to UNPCKHPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpackhi_pd` `__m128d _mm_unpackhi_pd(__m128d __a, __m128d __b)`	`UNPCKHPD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Moving the high double down#