UNPCKHPS instruction (SSE)

UNPCKHPS interleaves the upper halves of two vectors of singles, giving (a2, b2, a3, b3): the first operand’s elements keep the even positions, and the lower halves are ignored. UNPCKLPS, its low-half twin, describes the family; UNPCKHPD works on doubles, and VUNPCKHPS within each 128-bit lane. The legacy form writes over its first operand, keeps bits 128 and up of the register (see SSE and AVX), and its memory operand must be aligned to 16 bytes; of those 16, it uses the upper eight.

Zen 5’s recorded unpckhps xmm12, xmmword ptr [mem] put elements 2 and 3 of XMM12 in positions 0 and 2 and the two singles at bytes 8 to 15 of memory in positions 1 and 3, and unpckhps xmm4, xmm4 doubled each of the upper two elements.

Bringing the upper half down

With one register, the instruction moves elements 2 and 3 into the low half, where scalar instructions see them. In our builds at -O2, GCC 14 adds the four elements of a __m128, v[0] + v[1] + v[2] + v[3] in C’s order, with ADDSS, taking element 2 from an UNPCKHPS of a copy and elements 1 and 3 from SHUFPS; Clang 23 brings element 2 down with UNPCKHPD instead, moving the upper 64 bits as one. In GCC’s loop that merges two float arrays into pairs, each two input vectors give one UNPCKLPS and one UNPCKHPS, while Clang avoids the high unpack by loading half vectors. Widening needs no unpack: CVTPS2PD converts the low two singles, and GCC moves the upper two down with MOVHLPS first.

AMD’s spreadsheet for Zen 5 lists UNPCKHPS like UNPCKLPS: one macro-op with a latency of 1 cycle, on all four vector pipes.

Forms

Every encoding of UNPCKHPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`UNPCKHPS xmm, m128` UNPCKHPS_XMMps_MEMdq	`NP 0F 15 /r`	SSE
`UNPCKHPS xmm, xmm` UNPCKHPS_XMMps_XMMdq	`NP 0F 15 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the high singles of both sources alternate in the result, those of xmm1 in the even places.

Result singles 3 to 0: b3, a3, b2, a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(4):
    j = i // 2 + 2
    if i % 2 == 0:
        xmm1.d[i] = src1.d[j]
    else:
        xmm1.d[i] = src2.d[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`UNPCKHPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to UNPCKHPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpackhi_ps` `__m128 _mm_unpackhi_ps(__m128 __a, __m128 __b)`	`UNPCKHPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Bringing the upper half down#