UNPCKLPD instruction (SSE2)

UNPCKLPD builds a pair from the low double of each operand: the first operand’s low double stays in place and the second’s goes above it, so _mm_unpacklo_pd(a, b) gives a[0] in element 0 and b[0] in element 1. The high doubles are ignored; UNPCKHPD pairs those. It is the double-precision member of the unpack family that PUNPCKLBW describes, and VUNPCKLPD does the same in each 128-bit lane of a wider register.

Two points of the legacy form are easy to miss. The memory form reads 16 bytes and must find them aligned to 16 bytes, although only the low eight are used; and the result keeps bits 128 and up of the register (see SSE and AVX). Zen 5’s recorded unpcklpd xmm7, xmmword ptr [mem] put the first eight bytes of memory in the high double and ignored the next eight, and unpcklpd xmm4, xmm4 copied the low double into both halves.

In baseline code

That last case is the common one: MOVDDUP, the broadcast of a double, arrives only with SSE3, so for the default target GCC 14 at -O2 writes _mm_set1_pd(x) as unpcklpd xmm0, xmm0, and _mm_set_pd(b, a) as UNPCKLPD of the two registers. Clang 23 prefers MOVLHPS for the same moves, the same result with no 66 prefix, and uses UNPCKLPD in vectorized loops: to broadcast a scalar before a vectorized loop of b[i] * s, and with UNPCKHPD to split an array of complex numbers into real and imaginary parts.

With -march=x86-64-v2, which includes SSE3, both compilers broadcast a double loaded from memory with MOVDDUP, and Clang broadcasts a register that way too; GCC keeps unpcklpd xmm0, xmm0 for a register, even for _mm_movedup_pd. For the other half, the horizontal sum v[0] + v[1] of a __m128d uses UNPCKHPD in both compilers, which moves the high double down.

Forms

Every encoding of UNPCKLPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`UNPCKLPD xmm, m128` UNPCKLPD_XMMpd_MEMdq	`66 0F 14 /r`	SSE2
`UNPCKLPD xmm, xmm` UNPCKLPD_XMMpd_XMMq	`66 0F 14 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the low doubles of both sources alternate in the result, those of xmm1 in the even places.

Result doubles 1 to 0: b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(2):
    j = i // 2
    if i % 2 == 0:
        xmm1.q[i] = src1.q[j]
    else:
        xmm1.q[i] = src2.q[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`UNPCKLPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to UNPCKLPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_movelh_ps` `__m128 _mm_movelh_ps(__m128 __a, __m128 __b)`	`UNPCKLPD xmm, xmm` Legacy -msse
`_mm_set_pd` `__m128d _mm_set_pd(double __w, double __x)`	`UNPCKLPD xmm, xmm` Legacy -msse2
`_mm_setr_pd` `__m128d _mm_setr_pd(double __w, double __x)`	`UNPCKLPD xmm, xmm` Legacy -msse2
`_mm_unpacklo_pd` `__m128d _mm_unpacklo_pd(__m128d __a, __m128d __b)`	`UNPCKLPD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In baseline code#