UNPCKLPS instruction (SSE)

UNPCKLPS interleaves the low halves of two vectors of singles: from (a0, a1, a2, a3) and (b0, b1, b2, b3) it makes (a0, b0, a1, b1), the first operand’s elements keeping the even positions. The upper two elements of each operand are ignored; UNPCKHPS interleaves those. With one register as both operands it doubles each low element, giving (a0, a0, a1, a1). UNPCKLPD is the double-precision member of the family, and VUNPCKLPS does the same within each 128-bit lane.

Zen 5’s recorded cases: unpcklps xmm4, xmm4 doubled the two low singles, and unpcklps xmm7, xmmword ptr [mem] placed the first two singles of memory in elements 1 and 3, between XMM7’s own elements 0 and 1. The memory form reads 16 bytes, which must be aligned to 16, although it uses only the first eight. Like other legacy SSE instructions it writes over its first operand and keeps bits 128 and up of the register (see SSE and AVX).

Interleaving and building vectors

In our builds at -O2 for the default target, GCC 14 merges two float arrays into one of pairs, xy[2*i] = x[i]; xy[2*i+1] = y[i], with UNPCKLPS for the first two pairs and UNPCKHPS for the next two, from the same two vectors; Clang 23 loads eight bytes of each array at a time with MOVSD and needs only UNPCKLPS. _mm_set_ps from four floats in registers is two UNPCKLPS and a MOVLHPS in both compilers; with -march=x86-64-v2 Clang switches to three INSERTPS while GCC keeps the unpacks.

Intel’s optimization manual turns arrays of x, y, z and w values back into structures with UNPCKLPS, UNPCKHPS and the half moves MOVLHPS and MOVHLPS (Section 7.5.1.3). AMD’s spreadsheet for Zen 5 gives UNPCKLPS a latency of 1 cycle on all four vector pipes.

Forms

Every encoding of UNPCKLPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`UNPCKLPS xmm, m128` UNPCKLPS_XMMps_MEMdq	`NP 0F 14 /r`	SSE
`UNPCKLPS xmm, xmm` UNPCKLPS_XMMps_XMMq	`NP 0F 14 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the low singles of both sources alternate in the result, those of xmm1 in the even places.

Result singles 3 to 0: b1, a1, b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(4):
    j = i // 2
    if i % 2 == 0:
        xmm1.d[i] = src1.d[j]
    else:
        xmm1.d[i] = src2.d[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`UNPCKLPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to UNPCKLPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpacklo_ps` `__m128 _mm_unpacklo_ps(__m128 __a, __m128 __b)`	`UNPCKLPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Interleaving and building vectors#