x86-64.net

Instruction

UWRMSR

Writes a model-specific register from user mode, if the operating system allows that register in its user-MSR bitmap.

Extensions
Forms
4 (1 Legacy, 1 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of UWRMSR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
UWRMSR r64, r64 64-bit mode only UWRMSR_GPR64u64_GPR64u64F3 0F 38 F8 /rUSER_MSR
UWRMSR imm32, r64 64-bit mode only UWRMSR_IMM32_GPR64u64VEX.LZ.F3.MAP7.W0 F8 /0 idUSER_MSR
UWRMSR r64, r64 UWRMSR_GPR64u64_GPR64u64_APXEVEX.LLZ.F3.MAP4.W0 F8 /rAPX_F + USER_MSR
UWRMSR imm32, r64 UWRMSR_IMM32_GPR64u64_APXEVEX.LLZ.F3.MAP7.W0 F8 /0 idAPX_F + USER_MSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to UWRMSR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_uwrmsr void _uwrmsr(unsigned long long __A, unsigned long long __B)

UWRMSR r64, r64 Legacy -musermsr

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
USER_MSR

USER_MSR
CPUID.(EAX=07H,ECX=1):EDX[15] USER_MSR

Clearwater Forest
APX_F_USER_MSR

APX_F + USER_MSR
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=1):EDX[15] USER_MSR

None yet: XED lists these instructions only under its placeholder for future processors.

More USER_MSR instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.