Instruction
V4FMADDPS
Performs four fused multiply-adds of packed singles in a row, each with the next of four ZMM registers and the next single from memory.
Only Knights Mill, the last Xeon Phi processor, has this instruction; no other Intel processor supports it.
- Extensions
- Forms
- 1 (1 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
V4FMADDPS zmm {k}{z}, zmm+3, m128
V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | EVEX.512.F2.0F38.W0 9A /r | AVX512_4FMAPS |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
if not cpuid_leaf(7, 0)[3] >> 3 & 1:
fault(UD) # CPUID: no AVX512-4FMAPS
for i in range(16):
if k1[i]: # 1 without a write mask
r = zmm1.f32[i]
for j in range(4): # zmm2+3, in turn
a = zmm2.group[j].f32[i]
r = fmadd(a, mem.f32[j], r)
zmm1.f32[i] = r
elif zeroing:
zmm1.f32[i] = 0
# else: zmm1.f32[i] keeps its value
# each step: r + a * mem.f32[j], rounded once
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 1 case. It ran where CPUID reported no AVX512-4FMAPS, and raised an exception.
Operands
| Operand | Kind | Action |
|---|---|---|
V4FMADDPS zmm {k}{z}, zmm+3, m128 | ||
zmm | explicit | read, write (masked) |
{k} | explicit | read (write mask) |
zmm+3 | explicit | read |
m128 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E2
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking; memory fault suppression; follows MXCSR
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX512_4FMAPS_512 | AVX512_4FMAPS | Knights Mill |
More AVX512_4FMAPS instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2D, page 8-4 (V4FMADDPS/
V4FNMADDPS)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.