Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of V4FNMADDSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
V4FNMADDSS xmm {k}{z}, xmm+3, m128 V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512EVEX.LIG.F2.0F38.W0 AB /rAVX512_4FMAPS

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 0)[3] >> 3 & 1:
    fault(UD)                    # CPUID: no AVX512-4FMAPS
if k1[0]:                        # 1 without a write mask
    r = xmm1.f32[0]
    for j in range(4):           # xmm2+3, in turn
        a = xmm2.group[j].f32[0]
        r = fnmadd(a, mem.f32[j], r)
    xmm1.f32[0] = r
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
# xmm1.d[1] to [3] keep their values
# each step: r - a * mem.f32[j], rounded once
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 1 case. It ran where CPUID reported no AVX512-4FMAPS, and raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
V4FNMADDSS xmm {k}{z}, xmm+3, m128
xmmexplicitread, write (masked)
{k}explicitread (write mask)
xmm+3explicitread
m128explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms
write masking; memory fault suppression; follows MXCSR

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512_4FMAPS_SCALAR

AVX512_4FMAPS
CPUID.(EAX=07H,ECX=0):EDX[3] AVX512_4FMAPS

Knights Mill

More AVX512_4FMAPS instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2D, page 8-6 (V4FMADDSS/V4FNMADDSS)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.