VADDBF16

VADDBF16 adds bfloat16 values element by element, 8, 16 or 32 pairs in an xmm, ymm or zmm register. A bfloat16 is the upper half of a single, with the same 8-bit exponent and 7 fraction bits, as VCVTNE2PS2BF16’s page explains. AVX512_BF16 only converted to the format and computed dot products with VDPBF16PS; AVX10.2 adds arithmetic on it, of which VADDBF16 is the plainest. Its opcode is 58h in EVEX map 5 with the 66 prefix and W0, the byte of VADDPH, which has no prefix. It takes a write mask and a value broadcast from 16 bits of memory, but no rounding mode and no {sae}, and there is no scalar form.

One fixed environment#

The AVX10.2 specification (revision 7.0) fixes the rules for VADDBF16 and the other basic operations: rounding to nearest even, denormal inputs read as zeros, denormal results flushed to zero, no floating-point exceptions, and MXCSR neither read nor written. So MXCSR.RC, DAZ, FTZ and the exception masks change nothing, and a signaling NaN does not fault. VSUBBF16, VMULBF16, VDIVBF16 and VSQRTBF16 differ from it only in the operation.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 vectorizes Z[i] = X[i] + Y[i] over global __bf16 arrays into VADDBF16 on zmm registers, the second source from memory, and its header defines _mm512_add_pbh as a plain vector addition. A single __bf16 sum is widened to singles by a 16-bit shift, added with VADDSS and narrowed with VCVTNEPS2BF16. The two paths disagree on denormals: with MXCSR at its default, 0080h + 0040h gives 00C0h in the scalar code, while VADDBF16 reads 0040h as zero and gives 0080h.

With -march=znver5, which has AVX512_BF16 but not AVX10.2, the loop widens with VPMOVZXWD and VPSLLD, adds with VADDPS and narrows with VCVTNEPS2BF16; with -march=x86-64-v4 it stays scalar and calls __truncsfbf2 for each element. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.bf16[i]
        b = src3.bf16[i]
        zmm1.bf16[i] = add(a, b)
    elif zeroing:
        zmm1.bf16[i] = 0
    # else: zmm1.bf16[i] keeps its value
# m16bcst: src3.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even; denormal inputs read as zero; denormal results flushed to zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VADDBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCMPBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions