VADDPD

VADDPD adds doubles, two to an xmm register, four to a ymm one and eight to a zmm one. It is ADDPD in VEX and EVEX encodings, which add what VADDPS shows for singles: a separate destination, the bits above the result cleared, and in EVEX a write mask, a rounding mode given in the instruction and a broadcast, here of one 64-bit double. Rounding and the invalid sums work as on the ADDPS page, with a double’s 53-bit significand.

A double constant in float code#

In C, 0.1 is a double, so a[i] = b[i] + 0.1 over arrays of floats is computed in double precision and rounded back. GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 do just that: each eight floats are widened in two halves by VCVTPS2PD, added by two VADDPD and narrowed again by two VCVTPD2PS, where b[i] + 0.1f is one VADDPS taking its operand from memory. For arrays of doubles, both use VADDPD on ymm registers; with -march=x86-64-v4, GCC moves to zmm registers and Clang stays with ymm.

Flushing to zero#

With MXCSR’s FTZ bit set and underflow masked, a result too small to be a normal double becomes a zero of its sign, and the underflow and precision flags are set (MULPS covers FTZ and DAZ). In a case recorded on Zen 5 with FTZ set and rounding toward +infinity, the smallest denormal, 2^-1074, added to itself gave +0 instead of 2^-1073, and so did -2^-1023 plus 2^-1022. The largest denormal plus the smallest normal, an exact normal sum, came back as it was, but set the denormal flag for its input, as DAZ was clear.

On Zen 5#

AMD’s Zen 5 guide lists VADDPD exactly as VADDPS: one macro-op on the pipes FP2 and FP3, a latency of 2 cycles and two per cycle at every width. A vector of doubles costs what a vector of singles does, for half as many additions.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f64[i]
        b = src3.f64[i]
        zmm1.f64[i] = add(a, b)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VADDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPS
• VADDSD
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS

All 253 AVX instructions

More AVX10.1 instructions

• KSHIFTLW
• KSHIFTRB
• KSHIFTRD
• KSHIFTRQ
• KSHIFTRW
• KTESTB
• KTESTD
• KTESTQ
• KTESTW
• KUNPCKBW
• KUNPCKDQ
• KUNPCKWD
• KXNORB
• KXNORD
• KXNORQ
• KXNORW
• KXORB
• KXORD
• KXORQ
• KXORW
• VADDPH
• VADDPS
• VADDSD
• VADDSH
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENC
• VAESENCLAST
• VALIGND
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8

All 686 AVX10.1 instructions