VADDPH

VADDPH adds half-precision values (IEEE 754’s binary16: a sign, 5 exponent bits and 10 fraction bits) element by element, 32 of them in a zmm register, twice as many as VADDPS. It is the plainest instruction of AVX512-FP16, which brought arithmetic to a format that F16C had only converted: before it, halves were widened to singles with VCVTPH2PS, added, and narrowed again. VADDSH adds the lowest element only.

Requirements and encoding#

The 512-bit form needs AVX512_FP16 (CPUID leaf 7, EDX bit 23), the xmm and ymm forms AVX512VL as well; Intel’s manual adds that AVX512-FP16 requires AVX512BW, whose instructions handle the 32-bit masks. AVX10.1 includes all of it. The FP16 instructions live in two new EVEX opcode maps, 5 and 6, so VADDPH is EVEX.MAP5 58h, the opcode byte of ADDPS in another map. Only the 512-bit register form takes a rounding mode in the instruction ({er}): AVX10.2 at first allowed it for ymm too, and revision 4.0 of its specification withdrew that.

A narrow range#

The largest finite half is 65504, the smallest normal one 2^-14, and only integers up to 2048 are all exact. Intel’s optimization manual warns that 16-bit integers converted to halves land near the top of that range, where almost any arithmetic overflows to infinity, and suggests scaling them by a constant such as 1/256 (Section 18.5.7). Denormals cost nothing: the same chapter says FP16 arithmetic handles them at full speed and ignores MXCSR.DAZ and MXCSR.FTZ (Section 18.5.4). Those two bits are all it ignores: without {er}, VADDPH rounds as MXCSR.RC says and sets MXCSR’s exception flags, the denormal flag among them, as Intel’s page for the instruction lists. Complex numbers need no instruction of their own for adding: the real and imaginary parts are added as separate halves.

In compiled code#

With -march=sapphirerapids, Clang 23 at -O2 vectorizes c[i] = a[i] + b[i] over _Float16 arrays into VADDPH on ymm registers, with one operand from memory, checking at run time that pointer parameters do not overlap. GCC 14 does the same at -O2 only when the arrays cannot overlap and a constant count leaves no remainder: 1,024 elements of global arrays or through restrict pointers. Pointers without restrict keep its loop on VADDSH, one element at a time, even for that count, and so does a count known only at run time or one such as 1,001, even over global arrays. At -O3 it vectorizes them all, with an overlap check where it needs one and VADDSH for the remainder. Without AVX512-FP16, as with -march=znver5, both compilers convert each operand with VCVTPH2PS, add singles and narrow the sum with VCVTPS2PH; the page’s processor table shows which processors report the extension.

In the optimization guide

What the optimization guide says about VADDPH, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: AVX-512 FP16 adds and multiplies 32 half-precision values per 512-bit register with a latency of four cycles; division and square root take about 31. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.f16[i]
        b = src3.f16[i]
        zmm1.f16[i] = add(a, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VADDPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• KSHIFTRB
• KSHIFTRD
• KSHIFTRQ
• KSHIFTRW
• KTESTB
• KTESTD
• KTESTQ
• KTESTW
• KUNPCKBW
• KUNPCKDQ
• KUNPCKWD
• KXNORB
• KXNORD
• KXNORQ
• KXNORW
• KXORB
• KXORD
• KXORQ
• KXORW
• VADDPD
• VADDPS
• VADDSD
• VADDSH
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENC
• VAESENCLAST
• VALIGND
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2

All 686 AVX10.1 instructions