VADDPS

VADDPS is ADDPS in VEX and EVEX encodings. The ADDPS page covers the rounding, the tie rule and the invalid sums; this one covers what only the new encodings do, as the cases recorded on Zen 5 show it.

• The VEX forms write a third register and clear everything above the result: a 128-bit VADDPS left bits 128 to 511 of its destination zero, whatever they held.
• The EVEX forms write under a mask register, and an element whose mask bit is clear is not computed at all. With the invalid exception unmasked, vaddps zmm9{k2}, zmm9, zmm14 added 1 and 2 in the eight selected elements and left signaling NaNs in the other eight alone, without #XM.

Rounding given in the instruction#

Between 512-bit registers, an EVEX VADDPS can carry its own rounding mode, {rn-sae}, {rd-sae}, {ru-sae} or {rz-sae}, which replaces MXCSR.RC for that instruction. Zen 5 added 3 and 0.1 to 3.0999999 under MXCSR’s round to nearest, and to 3.10000014 under {ru-sae} while MXCSR asked to round toward zero. The sae part suppresses every exception: with all of them unmasked (MXCSR 0) and signaling NaNs among the inputs, {rn-sae} returned the NaNs quieted, took no #XM and set no flag.

Compilers#

For a[i] = b[i] + c[i] over 1,024 floats, GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 add ymm registers and take one operand straight from memory, which the VEX form allows at any alignment. With -march=x86-64-v4 GCC uses zmm registers and Clang stays with ymm; for -march=znver5 both use zmm, the width that AMD’s Zen 5 guide recommends, as that processor’s data paths are 512 bits wide (Section 2.11.2). The guide lists VADDPS as one macro-op with a latency of 2 cycles at every width.

In the optimization guide

What the optimization guide says about VADDPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Latency, throughput and dependency chains: Splitting a reduction such as the sum of an array over several accumulators lets as many operations run at once as there are accumulators.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f32[i]
        b = src3.f32[i]
        zmm1.f32[i] = add(a, b)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VADDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPD
• VADDSD
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS

All 253 AVX instructions

More AVX10.1 instructions

• KSHIFTRD
• KSHIFTRQ
• KSHIFTRW
• KTESTB
• KTESTD
• KTESTQ
• KTESTW
• KUNPCKBW
• KUNPCKDQ
• KUNPCKWD
• KXNORB
• KXNORD
• KXNORQ
• KXNORW
• KXORB
• KXORD
• KXORQ
• KXORW
• VADDPD
• VADDPH
• VADDSD
• VADDSH
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENC
• VAESENCLAST
• VALIGND
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4

All 686 AVX10.1 instructions