VADDSD

VADDSD is ADDSD in VEX and EVEX encodings: the sum of the low doubles of its two sources, with the high double copied from the first source and the bits above 127 cleared. VADDSS covers what the encodings change, from the third register to the vector length bit, and the ADDSD page shows why compilers keep the order of a sum of doubles. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1.

A sum computed either way#

For c > 0 ? a + b : a over doubles, GCC 14 at -O2 branches with -march=x86-64-v3 and x86-64-v4: VCOMISD against a zeroed register, and VADDSD only where c is positive. Clang 23 adds first, vaddsd xmm1, xmm0, xmm1, keeping a in XMM0, and then selects: with VCMPLTSD and VBLENDVPD for v3, and for v4 with VCMPLTSD into K1 and a masked vmovsd xmm0{k1}, xmm0, xmm1. Clang’s addition runs whatever c is, so its MXCSR flags are raised even when the sum is thrown away.

On Zen 5#

• vaddsd xmm8, xmm15, xmm0, under MXCSR 3FC0H (round down, DAZ set), added the negative denormal 8008000000000000H to the smallest normal double and returned that normal unchanged with no flag: DAZ read the denormal as -0, where the exact sum is the denormal 2^-1023.
• vaddsd xmm17{k1}{z}, xmm30, qword ptr [mem], with bit 0 of K1 clear, zeroed the low double and took the high one, the largest denormal, from XMM30, a register only EVEX can name. It came through unchanged although MXCSR (FFC0H) had FTZ and DAZ set: copied elements are not operands.

AMD’s latency spreadsheet for Zen 5 lists the VEX and the EVEX rows at 2 cycles on pipes FP2 and FP3, the figures of ADDSD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f64[0]
    b = src3.f64[0]
    xmm1.f64[0] = add(a, b)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VADDSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPD
• VADDPS
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS

All 253 AVX instructions

More AVX10.1 instructions

• KSHIFTRQ
• KSHIFTRW
• KTESTB
• KTESTD
• KTESTQ
• KTESTW
• KUNPCKBW
• KUNPCKDQ
• KUNPCKWD
• KXNORB
• KXNORD
• KXNORQ
• KXNORW
• KXORB
• KXORD
• KXORQ
• KXORW
• VADDPD
• VADDPH
• VADDPS
• VADDSH
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENC
• VAESENCLAST
• VALIGND
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2

All 686 AVX10.1 instructions