VADDSH

VADDSH adds the low half-precision values of its two sources and copies bits 127:16 from the first source, clearing the destination above bit 127, as VADDSS does for singles. It is the scalar form of VADDPH, whose page covers the format, the CPUID bits and FP16’s two opcode maps: VADDSH is opcode 58h with the F3 prefix in EVEX map 5. Being EVEX-only, it takes a write mask on the one element, {er} for a rounding mode of its own and xmm16 to xmm31, and reads two bytes when its second source is in memory. It rounds by MXCSR.RC otherwise and reports invalid, overflow, underflow, precision and denormal like the packed form, while ignoring MXCSR.DAZ and FTZ (Intel’s optimization manual, Section 18.5.4). VSUBSH subtracts.

Where compilers use it#

_Float16 arithmetic on single values becomes VADDSH: at -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile x + y to one vaddsh xmm0, xmm0, xmm1. A sum over a _Float16 array keeps C’s order of additions, so both compilers chain VADDSH with each half read from memory, GCC unrolled 32 times and Clang 8 times; only with -ffast-math do they add 32 or 16 halves at a time with VADDPH and reduce at the end. GCC also uses VADDSH for the sum in a dot product whose products it computes with VMULPH. Such a sum held in a half stops growing early: past 2048, adding 1 changes nothing, since the spacing of halves there is 2.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VADDSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f16[0]
    b = src3.f16[0]
    xmm1.f16[0] = add(a, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VADDSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• KSHIFTRW
• KTESTB
• KTESTD
• KTESTQ
• KTESTW
• KUNPCKBW
• KUNPCKDQ
• KUNPCKWD
• KXNORB
• KXNORD
• KXNORQ
• KXNORW
• KXORB
• KXORD
• KXORQ
• KXORW
• VADDPD
• VADDPH
• VADDPS
• VADDSD
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENC
• VAESENCLAST
• VALIGND
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4

All 686 AVX10.1 instructions