x86-64.net

Instruction

VADDSS

Adds the low singles; the other elements come from the first source.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

VADDSS is ADDSS in VEX and EVEX encodings: the sum of the low singles of its two sources, with singles 1 to 3 copied from the first source and the bits above 127 cleared. ADDSS’s page covers the edge cases, and VSQRTSS the write mask on the low single and a rounding mode on xmm registers. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1. There is no wider form: Intel’s opcode table ignores VEX.L but its text asks for L = 0, warning that L = 1 may behave differently across generations; AMD’s table leaves L a don’t-care without that warning.

A third register instead of a copy

(a + b) * (a - b) over floats needs both a and b after the sum. At the x86-64 baseline, in our builds at -O2, GCC 14 and Clang 23 first copy a with MOVAPS, since ADDSS and SUBSS each overwrite an operand; with -march=x86-64-v3 or x86-64-v4 both put the sum in a third register, vaddss xmm2, xmm0, xmm1, and need no copy: three instructions in all. A running sum over a global array stays a chain of vaddss xmm0, xmm0, dword ptr [...], in the order of the source.

On Zen 5

  • With MXCSR at 9FC0H (round to nearest, FTZ and DAZ set), 1 plus 1.5 times 2^-24, read from memory, gave the next single after 1, 3F800001H; under 7FC0H (toward zero) the same sum gave 1. Both set PE.
  • Under DF80H (round up, FTZ set), the smallest denormal plus itself gave +0 and set UE and PE as well as DE, where ADDSS’s page shows the exact 2^-148 with FTZ clear.
  • The EVEX vaddss xmm1, xmm2, xmm3, {rz-sae} under 1F80H added -2^-127 to 2^-126 and returned the denormal 2^-127 without DE.
  • vaddss xmm17{k6}{z}, xmm30, xmm2, with bit 0 of K6 clear, zeroed the low single and set no IE, though XMM30 held a signaling NaN.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows 2 cycles on pipes FP2 and FP3, as for ADDSS. VADDSD is the double form.

Forms

Every encoding of VADDSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VADDSS xmm, xmm, m32 VADDSS_XMMdq_XMMdq_MEMdVEX.LIG.F3.0F.WIG 58 /rAVX
VADDSS xmm, xmm, xmm VADDSS_XMMdq_XMMdq_XMMdVEX.LIG.F3.0F.WIG 58 /rAVX
VADDSS xmm {k}{z}, xmm, xmm, {er} VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512EVEX.LIG.F3.0F.W0 58 /rAVX10.1 or AVX512F
VADDSS xmm {k}{z}, xmm, m32 VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512EVEX.LIG.F3.0F.W0 58 /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m32
xmm {k}{z}, xmm, m32		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm, {er}no mask, with a mask, with {er}		xmm {k}{z}, xmm, xmm, {er}zeroing
Sandy Bridge9 / 1p13 / 1p1
Haswell, Broadwell8 / 1p13 / 1p1
Skylake9 / 0.5p014 / 0.5p01
Skylake-SP, Ice Lake9 / 0.5p014 / 0.5p014 / 0.5p01
Alder Lake10 / 0.5p153 / 0.5p15
Sapphire Rapids10 / 0.5p153 / 0.5p154 / 0.5p15
Lunar Lake10 / 0.5V2 V33 / 0.33p135
Piledriver10 / 1.5FPFMA FPU05 / 1FPFMA FPU0
Zen, Zen 210 / 0.5FPU2 FPU33 / 0.5FPU2 FPU3
Zen 310 / 0.5FP2 FP33 / 0.5FP2 FP3
Zen 410 / 0.5FP2 FP33 / 0.5FP2 FP33 / 0.5FP2 FP3
Jaguar8 / 1FPA FPU03 / 1FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm2.
VADDSS: the low elementResult single 0 is computed from single 0 of xmm2 and xmm3; singles 3 to 1 are those of xmm2. Result singles 3 to 0: a3, a2, a1, a0+b0.0123xmm2a1k1a0+b0a1a2a3xmm10123xmm3or m32b

The write mask k1 applies to the low single: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result single 0 is computed from single 0 of xmm2 and xmm3; singles 3 to 1 are those of xmm2. Result singles 3 to 0: a3, a2, a1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f32[0]
    b = src3.f32[0]
    xmm1.f32[0] = add(a, b)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 74 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VADDSS xmm, xmm, xmm/m32
xmmexplicitwrite
xmmexplicitread
xmm/m32explicitread
VADDSS xmm {k}{z}, xmm, xmm/m32, {er}
xmmexplicitwrite (masked)
{k}explicitread (write mask)
xmmexplicitread
xmm/m32explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-3
EVEX forms
AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms
follows MXCSR
EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VADDSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_add_round_ss __m128 _mm_add_round_ss(__m128 A, __m128 B, const int R)

VADDSS xmm, xmm, xmm, {er} EVEX.LIG -mavx512f

_mm_add_ss __m128 _mm_add_ss(__m128 __a, __m128 __b)

VADDSS xmm, xmm, xmm VEX.LIG -mavxwith AVX enabled

_mm_mask_add_round_ss __m128 _mm_mask_add_round_ss(__m128 W, __mmask8 U, __m128 A, __m128 B, const int R)

VADDSS xmm {k}, xmm, xmm, {er} EVEX.LIG -mavx512f

_mm_mask_add_ss __m128 _mm_mask_add_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)

VADDSS xmm {k}, xmm, xmm EVEX.LIG -mavx512f

_mm_maskz_add_round_ss __m128 _mm_maskz_add_round_ss(__mmask8 U, __m128 A, __m128 B, const int R)

VADDSS xmm {k}{z}, xmm, xmm, {er} EVEX.LIG -mavx512f

_mm_maskz_add_ss __m128 _mm_maskz_add_ss(__mmask8 __U, __m128 __A, __m128 __B)

VADDSS xmm {k}{z}, xmm, xmm EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-24 (ADDSS)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit, 256-Bit, and 512-Bit Media Instructions (26568, rev. 3.27, July 2026)
  9. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.