VADDSUBPS instruction (AVX)

Forms

Every encoding of VADDSUBPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VADDSUBPS xmm, xmm, m128` VADDSUBPS_XMMdq_XMMdq_MEMdq	`VEX.128.F2.0F.WIG D0 /r`	AVX
`VADDSUBPS xmm, xmm, xmm` VADDSUBPS_XMMdq_XMMdq_XMMdq	`VEX.128.F2.0F.WIG D0 /r`	AVX
`VADDSUBPS ymm, ymm, m256` VADDSUBPS_YMMqq_YMMqq_MEMqq	`VEX.256.F2.0F.WIG D0 /r`	AVX
`VADDSUBPS ymm, ymm, ymm` VADDSUBPS_YMMqq_YMMqq_YMMqq	`VEX.256.F2.0F.WIG D0 /r`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Every single works alike: 4 and 8 singles in the xmm and ymm forms.

Result single i comes from single i of xmm2 and xmm3. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = ymm2.f32[i]
    b = src3.f32[i]
    if i % 2 == 0:
        ymm1.f32[i] = sub(a, b)
    else:
        ymm1.f32[i] = add(a, b)
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VADDSUBPS xmm, xmm, xmm/m128` `VADDSUBPS ymm, ymm, ymm/m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VADDSUBPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_addsub_ps` `__m128 _mm_addsub_ps(__m128 __a, __m128 __b)`	`VADDSUBPS xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_addsub_ps` `__m256 _mm256_addsub_ps(__m256 __a, __m256 __b)`	`VADDSUBPS ymm, ymm, ymm` VEX.256 -mavx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions