VAESENC

VAESENC runs one middle round of AES on every 128-bit lane of its second operand and XORs in the round key from the same lane of the third. The round itself is AESENC’s, whose page covers the cipher, the byte order and the use of the last round, VAESENCLAST. What changes is the form:

• VEX.128 (AES and AVX): one block, like AESENC, but with a separate destination, so the state survives, bits 128 and up of the register cleared, and a memory operand that need not be aligned. GCC 14 and Clang 23 emit it for the same _mm_aesenc_si128 once AVX is on.
• VEX.256 (VAES): two blocks.
• EVEX (VAES with AVX512F, plus AVX512VL below 512 bits, or with AVX10.1): xmm, ymm and zmm, up to four blocks, and registers 16 to 31. There is no masking and no embedded broadcast.

XED, whose data the requirements table shows, also asks the EVEX forms for the AES bit next to AVX512F; Intel’s SDM (revision 093) does not.

One key per lane#

Each lane takes its own round key, so encrypting four blocks with one key needs the key copied to all four lanes first. Intel’s optimization manual loads each round key with VBROADCASTI64X2 and runs eight blocks in two zmm registers, and reports up to 3.3 times the speed of AESENC (Section 19.1, Example 19-1). For _mm512_aesenc_epi128(s, _mm512_broadcast_i32x4(k)), GCC 14 and Clang 23 at -O2 with -march=znver5 load the key with VBROADCASTI32X4. The same manual names multi-buffer code as the other use: four unrelated streams, each with its own key schedule, in the four lanes.

Zen 5’s 22 recorded cases cover every form, the zmm ones with a different key in each lane, and agree with the page’s pseudocode.

Width on Zen 5#

AMD’s Zen 5 guide lists VAESENC with the same figures for every width: one macro-op, a latency of 4 cycles and two per cycle. A zmm VAESENC therefore does four blocks’ work for the cost of one xmm round, as long as there are enough independent blocks to keep it busy: AESENC’s page explains why CBC encryption cannot supply them. The 512-bit intrinsics need -mvaes with AVX-512 (for example -march=znver4, znver5 or icelake-server); -march=znver3 has VAES only for ymm registers.

In the optimization guide

What the optimization guide says about VAESENC, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Ice Lake to Rocket Lake

• Vectors and AVX-512: AES rounds run on ports 0 and 1, so existing AES-NI code can reach twice its old peak rate. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

# a middle round of the cipher, in each 128-bit lane
for i in range(VL // 128):
    s = sub_bytes(zmm2.dq[i])    # zmm2: the state
    s = shift_rows(s)
    s = mix_columns(s)
    zmm1.dq[i] = s ^ src3.dq[i]  # AddRoundKey, the lane's key
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VAESENC, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AES-NI instructions

• AESDEC
• AESDECLAST
• AESENC
• AESENCLAST
• AESIMC
• AESKEYGENASSIST
• VAESDEC
• VAESDECLAST
• VAESENCLAST
• VAESIMC
• VAESKEYGENASSIST

More VAES instructions

• VAESDEC
• VAESDECLAST
• VAESENCLAST

More AVX10.1 instructions

• KTESTW
• KUNPCKBW
• KUNPCKDQ
• KUNPCKWD
• KXNORB
• KXNORD
• KXNORQ
• KXNORW
• KXORB
• KXORD
• KXORQ
• KXORW
• VADDPD
• VADDPH
• VADDPS
• VADDSD
• VADDSH
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENCLAST
• VALIGND
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD

All 686 AVX10.1 instructions