x86-64.net

Instruction

VAESENCLAST

Performs the last round of AES encryption on each 128-bit lane with the round key of the matching lane.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VAESENCLAST that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VAESENCLAST xmm, xmm, xmm VAESENCLAST_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.WIG DD /rAES + AVX
VAESENCLAST xmm, xmm, m128 VAESENCLAST_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.WIG DD /rAES + AVX
VAESENCLAST ymm, ymm, ymm VAESENCLAST_YMMu128_YMMu128_YMMu128VEX.256.66.0F38.WIG DD /rVAES
VAESENCLAST ymm, ymm, m256 VAESENCLAST_YMMu128_YMMu128_MEMu128VEX.256.66.0F38.WIG DD /rVAES
VAESENCLAST xmm, xmm, xmm VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512EVEX.128.66.0F38.WIG DD /rAVX10.1 + VAES or VAES + AES + AVX512F + AVX512VL
VAESENCLAST xmm, xmm, m128 VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512EVEX.128.66.0F38.WIG DD /rAVX10.1 + VAES or VAES + AES + AVX512F + AVX512VL
VAESENCLAST ymm, ymm, ymm VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512EVEX.256.66.0F38.WIG DD /rAVX10.1 + VAES or VAES + AES + AVX512F + AVX512VL
VAESENCLAST ymm, ymm, m256 VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512EVEX.256.66.0F38.WIG DD /rAVX10.1 + VAES or VAES + AES + AVX512F + AVX512VL
VAESENCLAST zmm, zmm, zmm VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512EVEX.512.66.0F38.WIG DD /rAVX10.1 + VAES or VAES + AES + AVX512F
VAESENCLAST zmm, zmm, m512 VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512EVEX.512.66.0F38.WIG DD /rAVX10.1 + VAES or VAES + AES + AVX512F

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VAESENCLAST, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_aesenclast_si128 __m128i _mm_aesenclast_si128(__m128i __V, __m128i __R)

VAESENCLAST xmm, xmm, xmm VEX.128 -maes -mavxwith AVX enabled

_mm256_aesenclast_epi128 __m256i _mm256_aesenclast_epi128(__m256i __A, __m256i __B)

VAESENCLAST ymm, ymm, ymm VEX.256 -mvaes

VAESENCLAST ymm, ymm, ymm VEX.256 -mvaes -mavxwith AVX enabled

_mm512_aesenclast_epi128 __m512i _mm512_aesenclast_epi128(__m512i __A, __m512i __B)

VAESENCLAST zmm, zmm, zmm EVEX.512 -mavx512f -mvaes

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVXAES

AES + AVX
CPUID.01H:ECX[25] AES
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
VAES

VAES
CPUID.(EAX=07H,ECX=0):ECX[9] VAES

Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest
AVX512_VAES_128

AVX10.1 + VAES
CPUID.(EAX=07H,ECX=0):ECX[9] VAES
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

VAES + AES + AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[9] VAES
CPUID.01H:ECX[25] AES
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VAES_256

AVX10.1 + VAES
CPUID.(EAX=07H,ECX=0):ECX[9] VAES
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

VAES + AES + AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[9] VAES
CPUID.01H:ECX[25] AES
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VAES_512

AVX10.1 + VAES
CPUID.(EAX=07H,ECX=0):ECX[9] VAES
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

VAES + AES + AVX512F
CPUID.(EAX=07H,ECX=0):ECX[9] VAES
CPUID.01H:ECX[25] AES
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.