VAESIMC instruction (AES-NI)

Forms

Every encoding of VAESIMC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VAESIMC xmm, xmm` VAESIMC_XMMdq_XMMdq	`VEX.128.66.0F38.WIG DB /r`	AES + AVX
`VAESIMC xmm, m128` VAESIMC_XMMdq_MEMdq	`VEX.128.66.0F38.WIG DB /r`	AES + AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each 128-bit block of the result comes from the 128-bit block in the same place in each source.

Result 128-bit block i comes from 128-bit block i of xmm2. Result 128-bit blocks: r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

# a round key of the cipher made one for
# AESDEC, the equivalent inverse cipher's
xmm1.write(inv_mix_columns(src2))
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VAESIMC xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VAESIMC, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_aesimc_si128` `__m128i _mm_aesimc_si128(__m128i __V)`	`VAESIMC xmm, xmm` VEX.128 -maes -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVXAES` AES-NI	AES + AVX `CPUID.01H:ECX[25]` AES `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

VAESIMC