Extensions
Forms
2 (2 VEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VAESKEYGENASSIST that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VAESKEYGENASSIST xmm, xmm, imm8 VAESKEYGENASSIST_XMMdq_XMMdq_IMMbVEX.128.66.0F3A.WIG DF /r ibAES + AVX
VAESKEYGENASSIST xmm, m128, imm8 VAESKEYGENASSIST_XMMdq_MEMdq_IMMbVEX.128.66.0F3A.WIG DF /r ibAES + AVX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x1 = sub_word(src2.d[1])           # SubWord: each byte
x3 = sub_word(src2.d[3])           # through the S-box
xmm1.d[0] = x1
xmm1.d[1] = ror(x1, 8, 32) ^ imm8  # RotWord turns byte 1
xmm1.d[2] = x3                     # into byte 0; imm8 is
xmm1.d[3] = ror(x3, 8, 32) ^ imm8  # zero-extended
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VAESKEYGENASSIST xmm, xmm/m128, imm8
xmmexplicitwrite
xmm/m128explicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
avx-type-4

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

More AES-NI instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-58 (AESKEYGENASSIST)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.