VALIGND

VALIGND joins its first source above its second and extracts one register’s worth of doublewords starting at the element the immediate names. With an offset of 3 on ZMM registers, the result is elements 3 to 15 of the second source followed by elements 0 to 2 of the first. The operand order is that of PALIGNR, but the shift counts doublewords instead of bytes and runs across the whole register, not within each 128-bit lane as VPALIGNR does. VALIGNQ counts quadwords.

The offset wraps#

Only as many low bits of the immediate count as the element count needs: two for XMM, three for YMM, four for ZMM. Larger values wrap instead of shifting in zeros as PALIGNR does, so VALIGND never brings in zeros by itself. In the cases recorded on Zen 5, immediate 5 on XMM registers acted as 1, and FFh on YMM registers as 7. A shift that should bring in zeros takes a zeroed register as the second source. At -O2 with -march=x86-64-v4, GCC 14 passes _mm512_alignr_epi32(a, b, 17) to the assembler as 17, while Clang 23 reduces it to 1, the same instruction in effect.

Rotating and shifting by elements#

With the same register in both sources, VALIGND rotates it by whole elements across lanes. For a rotation of sixteen int by one written with __builtin_shufflevector, Clang 23 emits valignd zmm0, zmm0, zmm0, 1, and for a shift by one element that brings in a zero, VALIGND with a zeroed register and offset 15. GCC 14 uses VPERMD for the rotation and VPERMI2D for the shift, each with an index vector loaded from memory. The VPALIGNR page shows VALIGND in Clang’s sliding windows, and the VPSHLDD page how it helps shift a whole register by bits.

Masks and broadcast#

The write mask applies per doubleword of the result. A broadcast operand makes the second source one value repeated, and VALIGND then shifts copies of it in: in a recorded case with offset 3, the broadcast doubleword went to every selected element from 0 to 12, and the first three elements of the other source landed in 13 to 15.

AMD’s Zen 5 guide lists VALIGND as one macro-op with a latency of 2, 4 and 5 cycles for XMM, YMM and ZMM.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 32                # 4 in xmm, 8 in ymm, 16 in zmm
for i in range(n):
    j = i + (imm8 & n - 1)  # element j of zmm2:src3
    if k1[i]:
        if j < n:
            zmm1.d[i] = src3.d[j]
        else:
            zmm1.d[i] = zmm2.d[j - n]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VALIGND, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• KUNPCKDQ
• KUNPCKWD
• KXNORB
• KXNORD
• KXNORQ
• KXNORW
• KXORB
• KXORD
• KXORQ
• KXORW
• VADDPD
• VADDPH
• VADDPS
• VADDSD
• VADDSH
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENC
• VAESENCLAST
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD

All 686 AVX10.1 instructions