VALIGNQ

VALIGNQ is VALIGND counting quadwords: it joins its first source above its second and extracts one register’s worth of quadwords from the element the immediate names. That page compares it with PALIGNR and VPALIGNR and shows how a zeroed register makes a shift. Since a ZMM register holds 8 quadwords, only three bits of the immediate count at 512 bits, two at 256 and one at 128, and larger values wrap.

Recorded on Zen 5#

• The wrap. With FFh, valignq xmm17, xmm30, xmm2, 0xff acted as offset 1, giving the high quadword of XMM2 below the low one of XMM30, and valignq ymm0{k2}, ymm31, ymmword ptr [mem], 0xff as offset 3.
• Offset 5 at 512 bits. valignq zmm17{k7}, zmm30, zmm2, 0x5 computed quadwords 5 to 7 of ZMM2 followed by 0 to 4 of ZMM30 and wrote the five that E3h selects, 0, 1 and 5 to 7.
• Offset 0 returns the second source unchanged: with a qword bcst operand, the same mask wrote the one quadword to those five elements.

In compiled code#

Clang 23 at -O2 with -march=x86-64-v4 uses VALIGNQ for what __builtin_shufflevector writes as a window of two vectors of eight long long or double, as a rotation by one element and as a shift that brings in a zero from a zeroed register. GCC 14 loads an index vector for each instead and uses VPERMQ for the rotation and VPERMI2Q or VPERMI2PD for the others. In a loop over long long arrays, h[i] = g[i] + g[i+1], Clang loads each vector once and builds the shifted one with VALIGNQ on ymm registers, carrying the previous vector over; GCC loads the array a second time, eight bytes further on. As with VALIGND, GCC passes _mm512_alignr_epi64(a, b, 9) on as 9 and Clang reduces it to 1.

AMD’s Zen 5 latency spreadsheet gives VALIGNQ 2, 3 and 5 cycles for XMM, YMM and ZMM registers, where VALIGND takes 4 at YMM, and two per cycle on pipes FP1 and FP2. Zen 5’s 6 recorded cases cover the register, memory and broadcast forms at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 64                # 2 in xmm, 4 in ymm, 8 in zmm
for i in range(n):
    j = i + (imm8 & n - 1)  # element j of zmm2:src3
    if k1[i]:
        if j < n:
            zmm1.q[i] = src3.q[j]
        else:
            zmm1.q[i] = zmm2.q[j - n]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VALIGNQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• KUNPCKWD
• KXNORB
• KXNORD
• KXNORQ
• KXNORW
• KXORB
• KXORD
• KXORQ
• KXORW
• VADDPD
• VADDPH
• VADDPS
• VADDSD
• VADDSH
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENC
• VAESENCLAST
• VALIGND
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH

All 686 AVX10.1 instructions