Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VANDNPS inverts its first source and ANDs the result with the second: vandnps ymm0, ymm1, ymm2 computes NOT ymm1 AND ymm2. It is the VEX and EVEX form of ANDNPS and belongs to the family that VANDPS describes: bits only, no MXCSR, and an EVEX form that needs AVX512DQ. The inverted operand is the one that is easy to get wrong. In a case recorded on Zen 5, a first source of 00000001H and a second of FFFFFFFFH gave FFFFFFFEH; swapped, the result would have been 0. The intrinsic _mm256_andnot_ps(a, b) keeps the order, inverting a.

Clearing what a mask selects

With a compare result as the first source, VANDNPS zeroes the elements where the compare held and keeps the others. GCC 14 at -O2 with -march=x86-64-v3 compiles a[i] = b[i] < c[i] ? 0.0f : d[i] to VCMPLTPS and vandnps ymm0, ymm0, ymm1. Clang 23 reverses the compare instead, to VCMPNLTPS, and loads d[i] under it with VMASKMOVPS, which zeroes the other elements by itself. Both give d[i] when b[i] or c[i] is a NaN, as the C expression does. With -0.0 as the first source, VANDNPS clears the sign bits: GCC uses it that way for the fabsf in -fabsf(x) (see VORPS).

A zeroing idiom

VANDNPS of a register with itself gives zero whatever the register held, as vandnps xmm24, xmm3, xmm3 did on Zen 5 with the EVEX encoding. AMD’s Zen 5 guide lists that form among the zeroing idioms, next to VXORPS, which clear the destination without waiting for the source and take no cycles (Section 2.9.2).

Forms

Every encoding of VANDNPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VANDNPS xmm, xmm, m128 VANDNPS_XMMdq_XMMdq_MEMdqVEX.128.NP.0F.WIG 55 /rAVX
VANDNPS xmm, xmm, xmm VANDNPS_XMMdq_XMMdq_XMMdqVEX.128.NP.0F.WIG 55 /rAVX
VANDNPS ymm, ymm, m256 VANDNPS_YMMqq_YMMqq_MEMqqVEX.256.NP.0F.WIG 55 /rAVX
VANDNPS ymm, ymm, ymm VANDNPS_YMMqq_YMMqq_YMMqqVEX.256.NP.0F.WIG 55 /rAVX
VANDNPS xmm {k}{z}, xmm, xmm VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512EVEX.128.NP.0F.W0 55 /rAVX10.1 or AVX512DQ + AVX512VL
VANDNPS xmm {k}{z}, xmm, m128/m32bcst VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512EVEX.128.NP.0F.W0 55 /rAVX10.1 or AVX512DQ + AVX512VL
VANDNPS ymm {k}{z}, ymm, ymm VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512EVEX.256.NP.0F.W0 55 /rAVX10.1 or AVX512DQ + AVX512VL
VANDNPS ymm {k}{z}, ymm, m256/m32bcst VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512EVEX.256.NP.0F.W0 55 /rAVX10.1 or AVX512DQ + AVX512VL
VANDNPS zmm {k}{z}, zmm, zmm VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512EVEX.512.NP.0F.W0 55 /rAVX10.1 or AVX512DQ
VANDNPS zmm {k}{z}, zmm, m512/m32bcst VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512EVEX.512.NP.0F.W0 55 /rAVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128/m32bcst
xmm, xmm, xmm
xmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm
ymm, ymm, m256
ymm {k}{z}, ymm, m256/m32bcst
ymm, ymm, ymmzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m32bcst
Sandy Bridge, Haswell7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake7 / 0.5p0151 / 0.33p0158 / 0.5p0151 / 0.33p015
Skylake-SP, Ice Lake7 / 0.5p0151 / 0.33p0158 / 0.5p0151 / 0.33p0151 / 0.5p058 / 0.5p05
Alder Lake8 / 0.33p0151 / 0.33p0159 / 0.33p0151 / 0.33p015
Sapphire Rapids8 / 0.33p0151 / 0.33p0159 / 0.33p0151 / 0.33p0151 / 0.5p059 / 0.5p05
Lunar Lake7 / 2V0 V1 V2 V31 / 0.25V0 V1 V2 V38 / 2.33V0 V1 V2 V31 / 0.25V0 V1 V2 V3
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU37 / 1.5FPMAL2 / 1FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU2 FPU31 / 0.25FPU0 FPU1 FPU2 FPU38 / 0.5FPU0 FPU1 FPU2 FPU31 / 0.5FPU0 FPU1 FPU2 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU2 FPU31 / 0.25FPU0 FPU1 FPU2 FPU38 / 0.33FPU0 FPU1 FPU2 FPU31 / 0.25FPU0 FPU1 FPU2 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP3
Zen 48 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPA FPM FPU0 FPU11 / 0.5FPA FPM FPU0 FPU16 / 2FPA FPM FPU0 FPU11 / 1FPA FPM FPU0 FPU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.
VANDNPS: element by elementResult doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: ~a3&b3, unchanged (bit 2 of k1 is 0), ~a1&b1, ~a0&b0.0123xmm2a1110k1~a0&b0~a1&b1~a3&b3xmm10123xmm3or m128b

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of the last source.

Result doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: ~a3&b3, unchanged (bit 2 of k1 is 0), ~a1&b1, ~a0&b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = ~zmm2.d[i] & src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VANDNPS xmm, xmm, xmm/m128 VANDNPS ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VANDNPS xmm {k}{z}, xmm, xmm/m128/m32bcst VANDNPS ymm {k}{z}, ymm, ymm/m256/m32bcst VANDNPS zmm {k}{z}, zmm, zmm/m512/m32bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VANDNPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_andnot_ps __m128 _mm_andnot_ps(__m128 __a, __m128 __b)

VANDNPS xmm, xmm, xmm VEX.128 -mavxwith AVX enabled; Clang emits the equivalent VPANDN

_mm256_andnot_ps __m256 _mm256_andnot_ps(__m256 __a, __m256 __b)

VANDNPS ymm, ymm, ymm VEX.256 -mavx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512DQ_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512DQ_256
Same as AVX512DQ_128Same as AVX512DQ_128
AVX512DQ_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Same as AVX512DQ_128

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-66 (ANDNPS)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.