Instruction
VANDNPS
Computes the bitwise AND of the inverted first source with the second, as packed singles.
VANDNPS inverts its first source and ANDs the result with the second:
vandnps ymm0, ymm1, ymm2 computes NOT ymm1 AND ymm2. It is the VEX
and EVEX form of ANDNPS and belongs to the family that
VANDPS describes: bits only, no MXCSR, and an EVEX form
that needs AVX512DQ. The inverted operand is the one that is easy to get
wrong. In a case recorded on Zen 5, a first source of 00000001H and a
second of FFFFFFFFH gave FFFFFFFEH; swapped, the result would have
been 0. The intrinsic _mm256_andnot_ps(a, b) keeps the order,
inverting a.
Clearing what a mask selects
With a compare result as the first source, VANDNPS zeroes the elements
where the compare held and keeps the others. GCC 14 at -O2 with
-march=x86-64-v3 compiles a[i] = b[i] < c[i] ? 0.0f : d[i] to
VCMPLTPS and vandnps ymm0, ymm0, ymm1. Clang 23 reverses the compare
instead, to VCMPNLTPS, and loads d[i] under it with
VMASKMOVPS, which zeroes the other elements by
itself. Both give d[i] when b[i] or c[i] is a NaN, as the C expression
does. With -0.0 as the
first source, VANDNPS clears the sign bits: GCC uses it that way for
the fabsf in -fabsf(x) (see VORPS).
A zeroing idiom
VANDNPS of a register with itself gives zero whatever the register
held, as vandnps xmm24, xmm3, xmm3 did on Zen 5 with the EVEX
encoding. AMD’s Zen 5 guide lists that form among the zeroing idioms,
next to VXORPS, which clear the destination without waiting for the
source and take no cycles (Section 2.9.2).
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VANDNPS xmm, xmm, m128
VANDNPS_XMMdq_XMMdq_MEMdq | VEX.128.NP.0F.WIG 55 /r | AVX |
VANDNPS xmm, xmm, xmm
VANDNPS_XMMdq_XMMdq_XMMdq | VEX.128.NP.0F.WIG 55 /r | AVX |
VANDNPS ymm, ymm, m256
VANDNPS_YMMqq_YMMqq_MEMqq | VEX.256.NP.0F.WIG 55 /r | AVX |
VANDNPS ymm, ymm, ymm
VANDNPS_YMMqq_YMMqq_YMMqq | VEX.256.NP.0F.WIG 55 /r | AVX |
VANDNPS xmm {k}{z}, xmm, xmm
VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | EVEX.128.NP.0F.W0 55 /r | AVX10.1 or AVX512DQ + AVX512VL |
VANDNPS xmm {k}{z}, xmm, m128/m32bcst
VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | EVEX.128.NP.0F.W0 55 /r | AVX10.1 or AVX512DQ + AVX512VL |
VANDNPS ymm {k}{z}, ymm, ymm
VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | EVEX.256.NP.0F.W0 55 /r | AVX10.1 or AVX512DQ + AVX512VL |
VANDNPS ymm {k}{z}, ymm, m256/m32bcst
VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | EVEX.256.NP.0F.W0 55 /r | AVX10.1 or AVX512DQ + AVX512VL |
VANDNPS zmm {k}{z}, zmm, zmm
VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | EVEX.512.NP.0F.W0 55 /r | AVX10.1 or AVX512DQ |
VANDNPS zmm {k}{z}, zmm, m512/m32bcst
VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | EVEX.512.NP.0F.W0 55 /r | AVX10.1 or AVX512DQ |
Latency and throughput
| Model | xmm, xmm, m128xmm {k}{z}, xmm, m128/m32bcst | xmm, xmm, xmmxmm {k}{z}, xmm, xmmymm {k}{z}, ymm, ymm | ymm, ymm, m256ymm {k}{z}, ymm, m256/m32bcst | ymm, ymm, ymm | zmm {k}{z}, zmm, zmm | zmm {k}{z}, zmm, m512/m32bcst |
|---|---|---|---|---|---|---|
| Sandy Bridge, Haswell | 7 / 1p5 | 1 / 1p5 | 8 / 1p5 | 1 / 1p5 | ||
| Broadwell | 6 / 1p5 | 1 / 1p5 | 7 / 1p5 | 1 / 1p5 | ||
| Skylake | 7 / 0.5p015 | 1 / 0.33p015 | 8 / 0.5p015 | 1 / 0.33p015 | ||
| Skylake-SP, Ice Lake | 7 / 0.5p015 | 1 / 0.33p015 | 8 / 0.5p015 | 1 / 0.33p015 | 1 / 0.5p05 | 8 / 0.5p05 |
| Alder Lake | 8 / 0.33p015 | 1 / 0.33p015 | 9 / 0.33p015 | 1 / 0.33p015 | ||
| Sapphire Rapids | 8 / 0.33p015 | 1 / 0.33p015 | 9 / 0.33p015 | 1 / 0.33p015 | 1 / 0.5p05 | 9 / 0.5p05 |
| Lunar Lake | 7 / 2V0 V1 V2 V3 | 1 / 0.25V0 V1 V2 V3 | 8 / 2.33V0 V1 V2 V3 | 1 / 0.25V0 V1 V2 V3 | ||
| Piledriver | 7 / 1.5FPMAL | 2 / 0.5FPMAL FPU2 FPU3 | 7 / 1.5FPMAL | 2 / 1FPMAL FPU2 FPU3 | ||
| Zen | 8 / 0.5FPU0 FPU1 FPU2 FPU3 | 1 / 0.25FPU0 FPU1 FPU2 FPU3 | 8 / 0.5FPU0 FPU1 FPU2 FPU3 | 1 / 0.5FPU0 FPU1 FPU2 FPU3 | ||
| Zen 2 | 8 / 0.33FPU0 FPU1 FPU2 FPU3 | 1 / 0.25FPU0 FPU1 FPU2 FPU3 | 8 / 0.33FPU0 FPU1 FPU2 FPU3 | 1 / 0.25FPU0 FPU1 FPU2 FPU3 | ||
| Zen 3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | ||
| Zen 4 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 1 / 0.5FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 |
| Jaguar | 6 / 1FPA FPM FPU0 FPU1 | 1 / 0.5FPA FPM FPU0 FPU1 | 6 / 2FPA FPM FPU0 FPU1 | 1 / 1FPA FPM FPU0 FPU1 | ||
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of the last source.
Result doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: ~a3&b3, unchanged (bit 2 of k1 is 0), ~a1&b1, ~a0&b0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 32):
if k1[i]: # 1 without a write mask
zmm1.d[i] = ~zmm2.d[i] & src3.d[i]
elif zeroing:
zmm1.d[i] = 0
# else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 10 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VANDNPS xmm, xmm, xmm/m128 VANDNPS ymm, ymm, ymm/m256 | ||
xmm, ymm | explicit | write |
xmm, ymm | explicit | read |
xmm/m128, ymm/m256 | explicit | read |
VANDNPS xmm {k}{z}, xmm, xmm/m128/m32bcst VANDNPS ymm {k}{z}, ymm, ymm/m256/m32bcst VANDNPS zmm {k}{z}, zmm, zmm/m512/m32bcst | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm, ymm, zmm | explicit | read |
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcst | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- VEX forms
avx-type-4- EVEX forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- EVEX forms
- write masking
- EVEX memory forms
- embedded broadcast (tuple Full); memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VANDNPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_andnot_ps
__m128 _mm_andnot_ps(__m128 __a, __m128 __b) |
|
_mm256_andnot_ps
__m256 _mm256_andnot_ps(__m256 __a, __m256 __b) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
More AVX instructions
- VADDPD
- VADDPS
- VADDSD
- VADDSS
- VADDSUBPD
- VADDSUBPS
- VANDNPD
- VANDPD
- VANDPS
- VBLENDPD
- VBLENDPS
- VBLENDVPD
- VBLENDVPS
- VBROADCASTF128
- VBROADCASTSD
- VBROADCASTSS
- VCMPPD
- VCMPPS
- VCMPSD
- VCMPSS
- VCOMISD
- VCOMISS
- VCVTDQ2PD
- VCVTDQ2PS
- VCVTPD2DQ
- VCVTPD2PS
- VCVTPS2DQ
- VCVTPS2PD
- VCVTSD2SI
- VCVTSD2SS
- VCVTSI2SD
- VCVTSI2SS
- VCVTSS2SD
- VCVTSS2SI
- VCVTTPD2DQ
- VCVTTPS2DQ
- VCVTTSD2SI
- VCVTTSS2SI
- VDIVPD
- VDIVPS
More AVX10.1 instructions
- KXNORD
- KXNORQ
- KXNORW
- KXORB
- KXORD
- KXORQ
- KXORW
- VADDPD
- VADDPH
- VADDPS
- VADDSD
- VADDSH
- VADDSS
- VAESDEC
- VAESDECLAST
- VAESENC
- VAESENCLAST
- VALIGND
- VALIGNQ
- VANDNPD
- VANDPD
- VANDPS
- VBLENDMPD
- VBLENDMPS
- VBROADCASTF32X2
- VBROADCASTF32X4
- VBROADCASTF32X8
- VBROADCASTF64X2
- VBROADCASTF64X4
- VBROADCASTI32X2
- VBROADCASTI32X4
- VBROADCASTI32X8
- VBROADCASTI64X2
- VBROADCASTI64X4
- VBROADCASTSD
- VBROADCASTSS
- VCMPPD
- VCMPPH
- VCMPPS
- VCMPSD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-66 (ANDNPS)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
- Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.