Instruction
VANDPD
Computes the bitwise AND of packed doubles.
VANDPD is the bitwise AND of two vectors, read as 64-bit elements. The bits are the same as those of VANDPS, whose page covers what the instruction is for (absolute values, copied signs, selecting with a compare result) and why its EVEX forms need AVX512DQ; nothing is rounded and no MXCSR flag can change. The element size matters only where the EVEX form looks at elements: a write mask selects doubles, and a broadcast from memory repeats one 64-bit value.
Which of the two compilers emit
GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 choose differently
for the same code on doubles:
fabs(b[i])is VANDPD with a broadcast 7FFFFFFFFFFFFFFFh in GCC and VANDPS with the same constant in Clang;copysign(b[i], c[i])is VANDNPD, VANDPD and VORPD in GCC and their PS forms in Clang;b[i] < c[i] ? b[i] : 0.0is VCMPPD and VANDPD in both, the compare’s all-ones elements keeping b and its zeros clearing it.
Clang picks the PS form where only bits are moved and keeps the PD form
next to a compare on doubles. With -march=x86-64-v4, the same select
needs no AND: both compilers compare into a mask register and copy b
with a zeroing VMOVAPD, and copysign becomes a
single VPTERNLOGQ.
Masks recorded on Zen 5
The masked cases show that elements, not bits, are selected:
vandpd zmm0{k5}, zmm31, zmm16, with k5 selecting elements 0 and 5 to
7, wrote the AND there and left elements 1 to 4 as zmm0 held them, and
vandpd zmm1{k7}, zmm2, qword bcst [mem] with an all-ones double
broadcast passed zmm2’s elements through where k7 selected them.
AMD’s Zen 5 guide lists VANDPD as it lists VANDPS, with a latency of 1 cycle on all four vector pipes.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VANDPD xmm, xmm, m128
VANDPD_XMMdq_XMMdq_MEMdq | VEX.128.66.0F.WIG 54 /r | AVX |
VANDPD xmm, xmm, xmm
VANDPD_XMMdq_XMMdq_XMMdq | VEX.128.66.0F.WIG 54 /r | AVX |
VANDPD ymm, ymm, m256
VANDPD_YMMqq_YMMqq_MEMqq | VEX.256.66.0F.WIG 54 /r | AVX |
VANDPD ymm, ymm, ymm
VANDPD_YMMqq_YMMqq_YMMqq | VEX.256.66.0F.WIG 54 /r | AVX |
VANDPD xmm {k}{z}, xmm, xmm
VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | EVEX.128.66.0F.W1 54 /r | AVX10.1 or AVX512DQ + AVX512VL |
VANDPD xmm {k}{z}, xmm, m128/m64bcst
VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | EVEX.128.66.0F.W1 54 /r | AVX10.1 or AVX512DQ + AVX512VL |
VANDPD ymm {k}{z}, ymm, ymm
VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | EVEX.256.66.0F.W1 54 /r | AVX10.1 or AVX512DQ + AVX512VL |
VANDPD ymm {k}{z}, ymm, m256/m64bcst
VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | EVEX.256.66.0F.W1 54 /r | AVX10.1 or AVX512DQ + AVX512VL |
VANDPD zmm {k}{z}, zmm, zmm
VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | EVEX.512.66.0F.W1 54 /r | AVX10.1 or AVX512DQ |
VANDPD zmm {k}{z}, zmm, m512/m64bcst
VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | EVEX.512.66.0F.W1 54 /r | AVX10.1 or AVX512DQ |
Latency and throughput
| Model | xmm, xmm, m128xmm {k}{z}, xmm, m128/m64bcst | xmm, xmm, xmmxmm {k}{z}, xmm, xmmymm {k}{z}, ymm, ymm | ymm, ymm, m256ymm {k}{z}, ymm, m256/m64bcst | ymm, ymm, ymm | zmm {k}{z}, zmm, zmm | zmm {k}{z}, zmm, m512/m64bcst |
|---|---|---|---|---|---|---|
| Sandy Bridge, Haswell | 7 / 1p5 | 1 / 1p5 | 8 / 1p5 | 1 / 1p5 | ||
| Broadwell | 6 / 1p5 | 1 / 1p5 | 7 / 1p5 | 1 / 1p5 | ||
| Skylake | 7 / 0.5p015 | 1 / 0.33p015 | 8 / 0.5p015 | 1 / 0.33p015 | ||
| Skylake-SP, Ice Lake | 7 / 0.5p015 | 1 / 0.33p015 | 8 / 0.5p015 | 1 / 0.33p015 | 1 / 0.5p05 | 8 / 0.5p05 |
| Alder Lake | 8 / 0.33p015 | 1 / 0.33p015 | 9 / 0.33p015 | 1 / 0.33p015 | ||
| Sapphire Rapids | 8 / 0.33p015 | 1 / 0.33p015 | 9 / 0.33p015 | 1 / 0.33p015 | 1 / 0.5p05 | 9 / 0.5p05 |
| Lunar Lake | 7 / 2V0 V1 V2 V3 | 1 / 0.25V0 V1 V2 V3 | 8 / 2.33V0 V1 V2 V3 | 1 / 0.25V0 V1 V2 V3 | ||
| Piledriver | 7 / 1.5FPMAL | 2 / 0.5FPMAL FPU2 FPU3 | 7 / 1.5FPMAL | 2 / 1FPMAL FPU2 FPU3 | ||
| Zen | 8 / 0.5FPU0 FPU1 FPU2 FPU3 | 1 / 0.25FPU0 FPU1 FPU2 FPU3 | 8 / 0.5FPU0 FPU1 FPU2 FPU3 | 1 / 0.5FPU0 FPU1 FPU2 FPU3 | ||
| Zen 2 | 8 / 0.33FPU0 FPU1 FPU2 FPU3 | 1 / 0.25FPU0 FPU1 FPU2 FPU3 | 8 / 0.33FPU0 FPU1 FPU2 FPU3 | 1 / 0.25FPU0 FPU1 FPU2 FPU3 | ||
| Zen 3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | ||
| Zen 4 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 1 / 0.5FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 |
| Jaguar | 6 / 1FPA FPM FPU0 FPU1 | 1 / 0.5FPA FPM FPU0 FPU1 | 6 / 2FPA FPM FPU0 FPU1 | 1 / 1FPA FPM FPU0 FPU1 | ||
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Every quadword works alike: 2, 4 and 8 quadwords in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m64bcst, one quadword from memory stands for every element of the last source.
Result quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: a1&b1, a0&b0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 64):
if k1[i]: # 1 without a write mask
zmm1.q[i] = zmm2.q[i] & src3.q[i]
elif zeroing:
zmm1.q[i] = 0
# else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 10 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VANDPD xmm, xmm, xmm/m128 VANDPD ymm, ymm, ymm/m256 | ||
xmm, ymm | explicit | write |
xmm, ymm | explicit | read |
xmm/m128, ymm/m256 | explicit | read |
VANDPD xmm {k}{z}, xmm, xmm/m128/m64bcst VANDPD ymm {k}{z}, ymm, ymm/m256/m64bcst VANDPD zmm {k}{z}, zmm, zmm/m512/m64bcst | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm, ymm, zmm | explicit | read |
xmm/m128/m64bcst, ymm/m256/m64bcst, zmm/m512/m64bcst | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- VEX forms
avx-type-4- EVEX forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- EVEX forms
- write masking
- EVEX memory forms
- embedded broadcast (tuple Full); memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VANDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm256_and_pd
__m256d _mm256_and_pd(__m256d __a, __m256d __b) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
More AVX instructions
- VADDPD
- VADDPS
- VADDSD
- VADDSS
- VADDSUBPD
- VADDSUBPS
- VANDNPD
- VANDNPS
- VANDPS
- VBLENDPD
- VBLENDPS
- VBLENDVPD
- VBLENDVPS
- VBROADCASTF128
- VBROADCASTSD
- VBROADCASTSS
- VCMPPD
- VCMPPS
- VCMPSD
- VCMPSS
- VCOMISD
- VCOMISS
- VCVTDQ2PD
- VCVTDQ2PS
- VCVTPD2DQ
- VCVTPD2PS
- VCVTPS2DQ
- VCVTPS2PD
- VCVTSD2SI
- VCVTSD2SS
- VCVTSI2SD
- VCVTSI2SS
- VCVTSS2SD
- VCVTSS2SI
- VCVTTPD2DQ
- VCVTTPS2DQ
- VCVTTSD2SI
- VCVTTSS2SI
- VDIVPD
- VDIVPS
More AVX10.1 instructions
- KXNORQ
- KXNORW
- KXORB
- KXORD
- KXORQ
- KXORW
- VADDPD
- VADDPH
- VADDPS
- VADDSD
- VADDSH
- VADDSS
- VAESDEC
- VAESDECLAST
- VAESENC
- VAESENCLAST
- VALIGND
- VALIGNQ
- VANDNPD
- VANDNPS
- VANDPS
- VBLENDMPD
- VBLENDMPS
- VBROADCASTF32X2
- VBROADCASTF32X4
- VBROADCASTF32X8
- VBROADCASTF64X2
- VBROADCASTF64X4
- VBROADCASTI32X2
- VBROADCASTI32X4
- VBROADCASTI32X8
- VBROADCASTI64X2
- VBROADCASTI64X4
- VBROADCASTSD
- VBROADCASTSS
- VCMPPD
- VCMPPH
- VCMPPS
- VCMPSD
- VCMPSH
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-69 (ANDPD)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
- Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.