VBCSTNEBF162PS

VBCSTNEBF162PS loads one bfloat16 value, 16 bits from memory, widens it to a single and writes that single to every doubleword of an XMM or a YMM register, 4 or 8 copies; the bits above are cleared. The widening puts the 16 bits above 16 zero bits, which is exact for every value: a denormal stays a denormal and a signaling NaN stays signaling, no exception is reported and MXCSR is neither read nor written. It is the broadcast form of the AVX-NE-CONVERT loads; the VCVTNEEBF162PS page explains the conversion and why these instructions take only memory: Crestmont, Intel’s optimization manual says, widens bfloat16 and FP16 in its load pipelines.

A broadcast for dot products#

One bfloat16 value applied to every element of a vector of singles, a weight or a scale, is the typical use. Before AVX-NE-CONVERT the same took a load, a shift by 16 and a VBROADCASTSS or VPBROADCASTD. In our builds that is still what the compilers do for C code: at -march=sierraforest, o[i] = (float)b[0] * o[i] over a __bf16 array becomes in Clang 23 a MOV, SHL by 16, VMOVD and VPBROADCASTD, and in GCC 14 a VPINSRW, a call to __extendbfsf2 and a VBROADCASTSS.

Encoding#

VEX.F3.0F38.W0 B1, at 128 and 256 bits, with a memory operand only; with 66 the same opcode is VBCSTNESH2PS, the FP16 broadcast. GCC 14 and Clang 23 compile _mm_bcstnebf16_ps(p) with -mavxneconvert to vbcstnebf162ps xmm0, word ptr [rdi]. Zen 5 lacks AVX-NE-CONVERT.

In the optimization guide

What the optimization guide says about VBCSTNEBF162PS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont widens BF16 and FP16 to single precision in the load pipelines, using no vector port.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = to_f32_ne(mem.bf16[0])
for i in range(VL // 32):
    ymm1.f32[i] = x
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBCSTNEBF162PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-NE-CONVERT instructions

• VBCSTNESH2PS
• VCVTNEEBF162PS
• VCVTNEEPH2PS
• VCVTNEOBF162PS
• VCVTNEOPH2PS
• VCVTNEPS2BF16