VBCSTNESH2PS

VBCSTNESH2PS loads one half-precision (FP16) value, 16 bits from memory, widens it to a single and writes the single to every doubleword of an XMM or a YMM register, 4 or 8 copies; the bits above are cleared. The conversion is exact, and a denormal half becomes the normal single it equals, not zero, whatever MXCSR.DAZ says. No exception is reported and MXCSR is neither read nor written. It is the FP16 twin of VBCSTNEBF162PS, and the broadcast form of VCVTNEEPH2PS, whose page compares these conversions with VCVTPH2PS.

Three instructions in one#

Without it, a half applied to a whole vector of singles takes three steps, and in our builds both compilers still take them: at -march=sierraforest, which has AVX-NE-CONVERT, GCC 14 and Clang 23 compile o[i] = (float)h[0] * o[i] over a _Float16 array to a VPINSRW of the half into a register, a VCVTPH2PS and a VBROADCASTSS, before the loop. Only the intrinsics _mm_bcstnesh_ps and _mm256_bcstnesh_ps reach the instruction: _mm256_bcstnesh_ps(p) with -mavxneconvert becomes vbcstnesh2ps ymm0, word ptr [rdi] in both. Crestmont, Intel’s optimization manual says, does the widening in its load pipelines, without the floating-point units.

Encoding#

VEX.66.0F38.W0 B1, at 128 and 256 bits; ModRM must name memory, since the conversion is part of the load. With F3 the same opcode is the bfloat16 broadcast, and B0 holds the four even and odd conversions. Intel lists AVX-NE-CONVERT for Sierra Forest, Grand Ridge, Arrow Lake H and Diamond Rapids; Zen 5 lacks it.

In the optimization guide

What the optimization guide says about VBCSTNESH2PS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont widens BF16 and FP16 to single precision in the load pipelines, using no vector port.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = to_f32_ne(mem.f16[0])
for i in range(VL // 32):
    ymm1.f32[i] = x
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBCSTNESH2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-NE-CONVERT instructions

• VBCSTNEBF162PS
• VCVTNEEBF162PS
• VCVTNEEPH2PS
• VCVTNEOBF162PS
• VCVTNEOPH2PS
• VCVTNEPS2BF16