VBLENDMPS

VBLENDMPS builds each single of its destination from one of two sources, chosen by a mask register: the second source where the mask bit is set, the first where it is clear, or zero there with {z}. It is VPBLENDMD under a floating-point name, the same selection on doublewords, and its page sets it against masked moves. It copies bits and does no arithmetic: the SDM lists no floating-point exception, and MXCSR stayed at 1F80h in all 6 cases recorded on Zen 5. The mask is typically written by VCMPPS, where the VEX form VBLENDVPS takes the sign bits of a compare result held in a vector register.

Recorded on Zen 5#

vblendmps zmm1{k2}, zmm2, dword bcst [mem] put the memory single into the nine elements where F2C9h, the low 16 bits of K2, has a bit set, and kept ZMM2’s in the other seven. At 128 bits only bits 3:0 count: vblendmps xmm0{k2}{z}, xmm31, dword bcst [mem] wrote the broadcast value to elements 0 and 3, by 9h, and zeros elsewhere.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 treat _mm512_mask_blend_ps as the integer blends: a masked VMOVAPS or VMOVUPS when they can, VBLENDMPS when the result must land in the other register. For o[i] = a[i] > b[i] ? c[i] : 5.0f over float arrays both emit VCMPPS into a mask and VBLENDMPS with c[i] from memory, where -march=x86-64-v3 gives VCMPPS into a vector and VBLENDVPS. A leaky ReLU, a[i] > 0 ? a[i] : 0.01f * a[i], splits them: GCC multiplies only the elements that need it, zero-masked, and blends with VBLENDMPS; Clang multiplies all and merges a[i] back with a masked VMOVAPS.

AMD’s Zen 5 latency spreadsheet gives VBLENDMPS one cycle and four per cycle on any of the four vector pipes, as VPBLENDMD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    else:
        zmm1.d[i] = zmm2.d[i]
# m32bcst: src3.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

opmask selects the source

Memory forms

embedded broadcast (tuple Full); memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• KXORD
• KXORQ
• KXORW
• VADDPD
• VADDPH
• VADDPS
• VADDSD
• VADDSH
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENC
• VAESENCLAST
• VALIGND
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH

All 686 AVX10.1 instructions