VBLENDPD instruction (AVX)

VBLENDPD picks each double of its result from one of two sources by a constant, as VBLENDPS does for singles: bit i of the immediate set takes element i from the third operand, clear from the second. With two doubles to an xmm register and four to a ymm one, it reads only bits 1:0 or 3:0 of the immediate. The cases recorded on Zen 5 show it:

vblendpd xmm1, xmm2, xmmword ptr [mem], 0x8A took element 1 from memory and element 0 from xmm2; bit 3 and bit 7 changed nothing.
vblendpd ymm0, ymm13, ymmword ptr [mem], 0x6C took elements 2 and 3 from memory and 0 and 1 from ymm13, and both forms cleared the destination above the result.

There is no EVEX form; under AVX-512, a mask register selects with VBLENDMPD, and a mask in a vector with VBLENDVPD.

Often written as VBLENDPS

A blend of doubles is also a blend of singles, with each bit of the immediate doubled: taking elements 1 and 3 of four doubles from the second source is 0Ah for VBLENDPD and 0CCh for VBLENDPS. Compilers choose differently. For __builtin_shufflevector(a, b, 0, 5, 2, 7) on four doubles, GCC 14 at -O2 with -mavx or -march=x86-64-v3 emits vblendpd ymm0, ymm1, ymm0, 5, with the sources swapped, and Clang 23 emits vblendps ymm0, ymm0, ymm1, 204. Setting element 0 of a vector, a[0] = x, is VBLENDPS with 3 in Clang, while GCC uses VMOVSD and VINSERTF128.

The two are not equal in cost on Zen 5: AMD’s guide lists VBLENDPD on two vector pipes, FP0 and FP1, against all four for VBLENDPS, with a latency of 1 cycle for both.

Forms

Every encoding of VBLENDPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VBLENDPD xmm, xmm, m128, imm8` VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb	`VEX.128.66.0F3A.WIG 0D /r ib`	AVX
`VBLENDPD xmm, xmm, xmm, imm8` VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb	`VEX.128.66.0F3A.WIG 0D /r ib`	AVX
`VBLENDPD ymm, ymm, m256, imm8` VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb	`VEX.256.66.0F3A.WIG 0D /r ib`	AVX
`VBLENDPD ymm, ymm, ymm, imm8` VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb	`VEX.256.66.0F3A.WIG 0D /r ib`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by immediate: each double comes from xmm3 where its bit of imm8 is 1, else from xmm2.

Example: imm8 = 0x01 (0000 0001 in binary). The wider forms go on with the next bits of imm8 for the higher elements.

Result doubles 1 to 0: a1, b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if imm8 >> i & 1:
        ymm1.q[i] = src3.q[i]
    else:
        ymm1.q[i] = ymm2.q[i]
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VBLENDPD xmm, xmm, xmm/m128, imm8` `VBLENDPD ymm, ymm, ymm/m256, imm8`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBLENDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_blend_pd` `__m128d _mm_blend_pd(__m128d V1, __m128d V2, const int M)`	`VBLENDPD xmm, xmm, xmm, imm8` VEX.128 -mavxwith AVX enabled
`_mm_move_sd` `__m128d _mm_move_sd(__m128d __a, __m128d __b)`	`VBLENDPD xmm, xmm, xmm, imm8` VEX.128 -mavxwith AVX enabled
`_mm256_blend_pd` `__m256d _mm256_blend_pd(__m256d V1, __m256d V2, const int M)`	`VBLENDPD ymm, ymm, ymm, imm8` VEX.256 -mavx
`_mm256_shuffle_f64x2` `__m256d _mm256_shuffle_f64x2(__m256d A, __m256d B, const int imm)`	`VBLENDPD ymm, ymm, ymm, imm8` VEX.256 -mavx512vl

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

Often written as VBLENDPS#