VBLENDPS

VBLENDPS picks each single of its result from one of two sources by a constant: bit i of the immediate set takes element i from the third operand, clear from the second. It is the VEX form of BLENDPS, with a separate destination and a 256-bit form that uses all eight bits of the immediate. The cases recorded on Zen 5 show both widths:

• vblendps ymm1, ymm2, ymm3, 0x96 took elements 1, 2, 4 and 7 from ymm3 and the rest from ymm2;
• vblendps xmm0, xmm13, xmmword ptr [mem], 0xEA took elements 1 and 3 from memory: the 128-bit form reads only bits 3:0 of the immediate, and it cleared bits 128 and up of the destination.

Where the choice is made at run time, by a mask in a vector, the instruction is VBLENDVPS; there is no EVEX form of either, so code for AVX-512 selects under a mask register with VBLENDMPS.

A blend is often a shuffle#

A shuffle of two vectors that leaves every element in its place is a blend. GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 compile __builtin_shufflevector(a, b, 0, 9, 2, 11, 4, 13, 6, 15) on eight floats to one VBLENDPS (GCC writes it with the sources swapped and the immediate inverted, 85 against Clang’s 170). Setting element 0 of a vector, a[0] = x, is vblendps ymm0, ymm0, ymm1, 1 in Clang, while GCC uses VMOVSS and VINSERTF128.

Intel’s optimization manual turns the same fact to account: in the Sandy Bridge microarchitecture the shuffles run only on port 5 and the blends also on port 0, and its 8x8 transpose of singles replaces eight of twelve VSHUFPS with VBLENDPS to relieve port 5 (Section 15.11.1). AMD’s Zen 5 guide lists VBLENDPS with a latency of 1 cycle on all four vector pipes, against two pipes for VBLENDVPS.

In the optimization guide

What the optimization guide says about VBLENDPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Shuffles and lane crossing: Intel’s shuffles share one port, so blends and shuffles done by loads relieve it; Ice Lake and Golden Cove add a second, in-lane one.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if imm8 >> i & 1:
        ymm1.d[i] = src3.d[i]
    else:
        ymm1.d[i] = ymm2.d[i]
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBLENDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPD
• VADDPS
• VADDSD
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS

All 253 AVX instructions