VBLENDVPD instruction (AVX)

In the optimization guide

What the optimization guide says about VBLENDVPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

Vectors and AVX2: The 256-bit variable blends are microcoded, one every 4 cycles.

Forms

Every encoding of VBLENDVPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VBLENDVPD xmm, xmm, m128, xmm` VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq	`VEX.128.66.0F3A.W0 4B /r /is4`	AVX
`VBLENDVPD xmm, xmm, xmm, xmm` VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq	`VEX.128.66.0F3A.W0 4B /r /is4`	AVX
`VBLENDVPD ymm, ymm, m256, ymm` VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq	`VEX.256.66.0F3A.W0 4B /r /is4`	AVX
`VBLENDVPD ymm, ymm, ymm, ymm` VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq	`VEX.256.66.0F3A.W0 4B /r /is4`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by vector: each double comes from xmm3 where the sign bit of the double in the same place of xmm4 is 1, else from xmm2.

Example sign bits of xmm4: 01. Every double of the wider forms works alike.

Result doubles 1 to 0: a1, b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if ymm4.q[i] >> 63:
        ymm1.q[i] = src3.q[i]
    else:
        ymm1.q[i] = ymm2.q[i]
# ymm4.q[i] >> 63: the sign bit of the element
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VBLENDVPD xmm, xmm, xmm/m128, xmm` `VBLENDVPD ymm, ymm, ymm/m256, ymm`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read
`xmm, ymm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBLENDVPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_blendv_pd` `__m128d _mm_blendv_pd(__m128d __V1, __m128d __V2, __m128d __M)`	`VBLENDVPD xmm, xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_blendv_pd` `__m256d _mm256_blendv_pd(__m256d __a, __m256d __b, __m256d __c)`	`VBLENDVPD ymm, ymm, ymm, ymm` VEX.256 -mavx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions