VBLENDVPS

VBLENDVPS is the VEX form of BLENDVPS, whose page explains why only the sign bit of each mask element counts and what that means for float masks. The VEX form changes where the mask comes from: instead of the implied XMM0, it is a fourth register, named in bits 7:4 of an immediate byte, so any of registers 0 to 15 can hold it. Both sources stay intact, and a 256-bit form blends eight singles. A case recorded on Zen 5 used one register for all three roles, vblendvps ymm4, ymm4, ymmword ptr [mem], ymm4: the elements of ymm4 with the sign bit set were replaced from memory, and the others kept.

In compiled code#

For r[i] = a[i] > b[i] ? a[i] : 0.5f over floats, GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 compare with VCMPLTPS into a ymm register and pass that register straight to VBLENDVPS as the mask, vblendvps ymm0, ymm2, ymm0, ymm1 in GCC, where BLENDVPS would need it moved to XMM0. _mm256_blendv_ps(a, b, mask) is one VBLENDVPS.

There is no EVEX form. With -march=x86-64-v4 the compare writes a mask register instead, and VBLENDMPS selects under it: on zmm registers in GCC and ymm in Clang. Being VEX-only, VBLENDVPS also cannot reach registers 16 to 31.

Cost#

Intel’s optimization manual notes that on Crestmont, whose vector units are 128 bits wide, the 256-bit VBLENDVPS is a microcoded flow with a latency of three cycles and a throughput of one every four cycles (Section 4.1.9.4). VBLENDVPD selects doubles by the sign bit of each quadword.

In the optimization guide

What the optimization guide says about VBLENDVPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit variable blends are microcoded, one every 4 cycles.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if ymm4.d[i] >> 31:
        ymm1.d[i] = src3.d[i]
    else:
        ymm1.d[i] = ymm2.d[i]
# ymm4.d[i] >> 31: the sign bit of the element
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBLENDVPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPD
• VADDPS
• VADDSD
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS

All 253 AVX instructions