Instruction
VBROADCASTF32X2
Copies a group of two singles (64 bits) from memory or a register to every such group of a vector.
- Extensions
- Forms
- 4 (4 EVEX)
- Data
- Intel XED v2026.08.23
VBROADCASTF32X2 takes two singles, the low 64 bits of an XMM register or of memory, and repeats the pair in every 64-bit slot of a YMM or ZMM register, under a mask of singles. It belongs to AVX512DQ (plus AVX512VL for YMM) and has no XMM destination. VBROADCASTI32X2 is the integer form, which does have one. Unmasked, the result is bit for bit what VBROADCASTSD gives from the same 64 bits; the difference is the mask, which can split a pair. VBROADCASTF32X4 repeats four singles.
Recorded on Zen 5
- A split pair.
vbroadcastf32x2 zmm14{k3}, qword ptr [mem], with AAEBh in the low 16 bits of K3, wrote the second single of memory in every odd element and the first only in elements 0 and 6, the even ones K3 selects; elements 2, 4, 8 and others kept their old values. - From a register, zero-masked.
vbroadcastf32x2 ymm14{k7}{z}, xmm8with E3h in K7 wrote elements 0, 1, 5, 6 and 7 from the low pair of XMM8, odd elements from the second single, zeroed elements 2 to 4 and cleared ZMM14 above bit 255. - Unmasked YMM. The EVEX form wrote four copies of the pair and cleared bits 511:256.
In compiled code
At -O2 with -march=x86-64-v4, GCC 14 compiles _mm512_broadcast_f32x2
to VBROADCASTF32X2, from memory or from a register, while Clang 23 emits
VBROADCASTSD for both, the same bits. With a write mask,
_mm256_mask_broadcast_f32x2, both use VBROADCASTF32X2. A loop over a
repeating pair, h[i] = f[i] * p2[i & 1], stays scalar in both.
AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2, two per cycle, for the YMM and ZMM forms.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VBROADCASTF32X2 ymm {k}{z}, xmm
VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 | EVEX.256.66.0F38.W0 19 /r | AVX10.1 or AVX512DQ + AVX512VL |
VBROADCASTF32X2 ymm {k}{z}, m64
VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 | EVEX.256.66.0F38.W0 19 /r | AVX10.1 or AVX512DQ + AVX512VL |
VBROADCASTF32X2 zmm {k}{z}, xmm
VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 | EVEX.512.66.0F38.W0 19 /r | AVX10.1 or AVX512DQ |
VBROADCASTF32X2 zmm {k}{z}, m64
VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 | EVEX.512.66.0F38.W0 19 /r | AVX10.1 or AVX512DQ |
Latency and throughput
| Model | ymm {k}{z}, xmmzmm {k}{z}, xmm | ymm {k}{z}, m64no maskzmm {k}{z}, m64no mask | ymm {k}{z}, m64with a mask, zeroing | zmm {k}{z}, m64with a mask, zeroing |
|---|---|---|---|---|
| Skylake-SP, Ice Lake | 3 / 1p5 | 8 / 0.5p015 | 8 / 0.5p015 | 8 / 0.5p015 |
| Sapphire Rapids | 3 / 1p5 | 8 / 0.33p2 p3 p10 | 9 / 0.33p015 | 9 / 0.5p05 |
| Zen 4 | 1 / 1FP1 | 8 / 1FP1 | 8 / 1FP1 | 8 / 1FP1 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Shown for the zmm form; the ymm form works the same on 8 singles. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.
Result singles 15 to 0: a1, unchanged (bit 14 of k1 is 0), a1, a0, a1, a0, a1, a0, a1, a0, a1, a0, a1, a0, a1, a0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 32):
if k1[i]:
zmm1.d[i] = src2.d[i % 2]
elif zeroing:
zmm1.d[i] = 0
# else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 4 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VBROADCASTF32X2 ymm {k}{z}, xmm/m64 VBROADCASTF32X2 zmm {k}{z}, xmm/m64 | ||
ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm/m64 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E6
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking
- Memory forms
- memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VBROADCASTF32X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm256_mask_broadcast_f32x2
__m256 _mm256_mask_broadcast_f32x2(__m256 __O, __mmask8 __M, __m128 __A) |
|
_mm256_maskz_broadcast_f32x2
__m256 _mm256_maskz_broadcast_f32x2(__mmask8 __M, __m128 __A) |
|
_mm512_broadcast_f32x2
__m512 _mm512_broadcast_f32x2(__m128 __A) |
|
_mm512_mask_broadcast_f32x2
__m512 _mm512_mask_broadcast_f32x2(__m512 __O, __mmask16 __M, __m128 __A) |
|
_mm512_maskz_broadcast_f32x2
__m512 _mm512_maskz_broadcast_f32x2(__mmask16 __M, __m128 __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX512DQ_256 | AVX10.1 or AVX512DQ + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6 |
AVX512DQ_512 | AVX10.1 or AVX512DQ | Same as AVX512DQ_256 |
More AVX10.1 instructions
- KXORQ
- KXORW
- VADDPD
- VADDPH
- VADDPS
- VADDSD
- VADDSH
- VADDSS
- VAESDEC
- VAESDECLAST
- VAESENC
- VAESENCLAST
- VALIGND
- VALIGNQ
- VANDNPD
- VANDNPS
- VANDPD
- VANDPS
- VBLENDMPD
- VBLENDMPS
- VBROADCASTF32X4
- VBROADCASTF32X8
- VBROADCASTF64X2
- VBROADCASTF64X4
- VBROADCASTI32X2
- VBROADCASTI32X4
- VBROADCASTI32X8
- VBROADCASTI64X2
- VBROADCASTI64X4
- VBROADCASTSD
- VBROADCASTSS
- VCMPPD
- VCMPPH
- VCMPPS
- VCMPSD
- VCMPSH
- VCMPSS
- VCOMISD
- VCOMISH
- VCOMISS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-12 (VBROADCAST)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.