Instruction
VBROADCASTF32X4
Copies a group of four singles (128 bits) from memory to every 128-bit block of a vector.
- Extensions
- Forms
- 2 (2 EVEX)
- Data
- Intel XED v2026.08.23
VBROADCASTF32X4 loads four singles, 16 bytes, from memory and repeats them in every 128-bit block of a YMM or ZMM register, under a mask of singles. It is VBROADCASTI32X4 under a floating-point name, and that page covers the forms; the bits are copied, not converted, so no SIMD exception can arise. It needs AVX512F, plus AVX512VL for the YMM form, and takes only a memory source. Unmasked on YMM registers it does what AVX’s VBROADCASTF128 does, and VBROADCASTF64X2 is the same load with a mask of quadwords.
Recorded on Zen 5
- Masked by singles.
vbroadcastf32x4 zmm9{k3}, xmmword ptr [mem], with AAEBh in the low 16 bits of K3, wrote the doublewords that K3 selects, each from its place within the 16 bytes, and kept the others: element 2 kept its old value while element 3 next to it took the fourth single of memory, a split that a mask of quadwords cannot make. - YMM.
{evex} vbroadcastf32x4 ymm9, xmmword ptr [mem]wrote two copies and cleared ZMM9 from bit 256 up.
In compiled code
GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile
_mm512_broadcast_f32x4 of a value in memory to VBROADCASTF32X4, and
Clang uses it as well for _mm512_broadcast_f64x2 without a mask,
where GCC keeps VBROADCASTF64X2. A loop that multiplies by a repeating
pattern of four floats, g[i] = f[i] * pf[i & 3], is not vectorized
by either compiler at -O2: both multiply one element at a time.
AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2 for the YMM and ZMM forms.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VBROADCASTF32X4 zmm {k}{z}, m128
VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 | EVEX.512.66.0F38.W0 1A /r | AVX10.1 or AVX512F |
VBROADCASTF32X4 ymm {k}{z}, m128
VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 | EVEX.256.66.0F38.W0 1A /r | AVX10.1 or AVX512F + AVX512VL |
Latency and throughput
| Model | zmm {k}{z}, m128no maskymm {k}{z}, m128no mask | zmm {k}{z}, m128with a mask, zeroing | ymm {k}{z}, m128with a mask, zeroing |
|---|---|---|---|
| Skylake-SP, Ice Lake | 8 / 0.5p015 | 8 / 0.5p015 | 8 / 0.5p015 |
| Sapphire Rapids | 8 / 0.33p2 p3 p10 | 9 / 0.5p05 | 9 / 0.33p015 |
| Zen 4 | 8 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Shown for the zmm form; the ymm form works the same on 8 singles. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.
Result singles 15 to 0: a3, unchanged (bit 14 of k1 is 0), a1, a0, a3, a2, a1, a0, a3, a2, a1, a0, a3, a2, a1, a0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 32):
if k1[i]:
zmm1.d[i] = mem.d[i % 4]
elif zeroing:
zmm1.d[i] = 0
# else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 2 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VBROADCASTF32X4 ymm {k}{z}, m128 VBROADCASTF32X4 zmm {k}{z}, m128 | ||
ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
m128 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E6
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking; memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VBROADCASTF32X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm256_mask_broadcast_f32x4
__m256 _mm256_mask_broadcast_f32x4(__m256 __O, __mmask8 __M, __m128 __A) |
|
_mm256_maskz_broadcast_f32x4
__m256 _mm256_maskz_broadcast_f32x4(__mmask8 __M, __m128 __A) |
|
_mm512_broadcast_f32x4
__m512 _mm512_broadcast_f32x4(__m128 __A) |
|
_mm512_mask_broadcast_f32x4
__m512 _mm512_mask_broadcast_f32x4(__m512 __O, __mmask16 __M, __m128 __A) |
|
_mm512_maskz_broadcast_f32x4
__m512 _mm512_maskz_broadcast_f32x4(__mmask16 __M, __m128 __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX512F_512 | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6 |
AVX512F_256 | AVX10.1 or AVX512F + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6 |
More AVX10.1 instructions
- KXORW
- VADDPD
- VADDPH
- VADDPS
- VADDSD
- VADDSH
- VADDSS
- VAESDEC
- VAESDECLAST
- VAESENC
- VAESENCLAST
- VALIGND
- VALIGNQ
- VANDNPD
- VANDNPS
- VANDPD
- VANDPS
- VBLENDMPD
- VBLENDMPS
- VBROADCASTF32X2
- VBROADCASTF32X8
- VBROADCASTF64X2
- VBROADCASTF64X4
- VBROADCASTI32X2
- VBROADCASTI32X4
- VBROADCASTI32X8
- VBROADCASTI64X2
- VBROADCASTI64X4
- VBROADCASTSD
- VBROADCASTSS
- VCMPPD
- VCMPPH
- VCMPPS
- VCMPSD
- VCMPSH
- VCMPSS
- VCOMISD
- VCOMISH
- VCOMISS
- VCOMPRESSPD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-12 (VBROADCAST)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.