VBROADCASTF32X8 instruction (AVX10.1)

VBROADCASTF32X8 loads 32 bytes, eight singles, from memory and repeats them in both 256-bit halves of a ZMM register, under a mask of singles. It exists only at 512 bits, has no register source, and needs AVX512DQ. Unmasked it gives the same bits as VBROADCASTF64X4, which needs only AVX512F; the two differ in the element size of the mask, as VBROADCASTI32X8 and VBROADCASTI64X4 do for integers. VBROADCASTF32X4 repeats 16 bytes.

Recorded on Zen 5

vbroadcastf32x8 zmm24{k1}, ymmword ptr [mem], with 32A0h in the low 16 bits of K1, wrote singles 5, 7, 9, 12 and 13 of ZMM24, each from the single of memory at the same place within its half: 5 and 13 both from single 5, 9 from single 1, 12 from single 4. The other eleven kept their values. This is the one case the fixture holds for the page.

In compiled code

At -O2 with -march=x86-64-v4, GCC 14 compiles _mm512_broadcast_f32x8 of a value in memory to VBROADCASTF32X8, and of a value in a register, which the instruction cannot take, to VSHUFF32X4 with the immediate 44h. Clang 23 emits VBROADCASTF64X4 for the memory form and VINSERTF64X4 for the register. With a write mask, _mm512_mask_broadcast_f32x8, both use VBROADCASTF32X8.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2, two per cycle, with a latency of 1 cycle.

Forms

Every encoding of VBROADCASTF32X8 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VBROADCASTF32X8 zmm {k}{z}, m256` VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512	`EVEX.512.66.0F38.W0 1B /r`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`zmm {k}{z}, m256`no mask	`zmm {k}{z}, m256`with a mask, zeroing
Skylake-SP, Ice Lake	8 / 0.5p015	8 / 0.5p015
Sapphire Rapids	8 / 0.33p2 p3 p10	9 / 0.5p05
Zen 4	8 / 0.5FP1 FP2	8 / 0.5FP1 FP2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Broadcast: 8 singles go to every 256-bit block of the result.

The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result singles 15 to 0: a7, unchanged (bit 14 of k1 is 0), a5, a4, a3, a2, a1, a0, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(16):
    if k1[i]:
        zmm1.d[i] = mem.d[i % 8]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VBROADCASTF32X8 zmm {k}{z}, m256`
`zmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms: write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBROADCASTF32X8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm512_broadcast_f32x8` `__m512 _mm512_broadcast_f32x8(__m256 __A)`	`VBROADCASTF32X8 zmm, m256` EVEX.512 -mavx512dqwhen __A comes from memory; Clang emits the equivalent VBROADCASTF64X4
`_mm512_mask_broadcast_f32x8` `__m512 _mm512_mask_broadcast_f32x8(__m512 __O, __mmask16 __M, __m256 __A)`	`VBROADCASTF32X8 zmm {k}, m256` EVEX.512 -mavx512dqwhen __A comes from memory
`_mm512_maskz_broadcast_f32x8` `__m512 _mm512_maskz_broadcast_f32x8(__mmask16 __M, __m256 __A)`	`VBROADCASTF32X8 zmm {k}{z}, m256` EVEX.512 -mavx512dqwhen __A comes from memory

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX512DQ_512

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

In compiled code#