x86-64.net

Instruction

VBROADCASTF64X2

Copies a group of two doubles (128 bits) from memory to every 128-bit block of a vector.

Extensions
Forms
2 (2 EVEX)
Data
Intel XED v2026.08.23

VBROADCASTF64X2 loads two doubles, 16 bytes, from memory and repeats them in every 128-bit block of a YMM or ZMM register, under a mask of quadwords. It is VBROADCASTI64X2 under a floating-point name, and that page covers the forms; nothing is converted, so no SIMD exception can arise. It came with AVX512DQ. VBROADCASTF32X4, from AVX512F, puts the same bytes in the same places under a mask of singles, so the two differ only when a mask is given; VBROADCASTF128 is the AVX form for YMM registers. It takes only a memory source.

Recorded on Zen 5

  • Two copies in a YMM register. {evex} vbroadcastf64x2 ymm14, xmmword ptr [mem] wrote the 16 bytes twice and cleared ZMM14 from bit 256 up.
  • Masked by quadwords. vbroadcastf64x2 zmm1{k1}, xmmword ptr [mem], with A0h in the low byte of K1, wrote only elements 5 and 7, each the second double of memory, and kept the other six quadwords of ZMM1.

In compiled code

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 differ on the intrinsic: _mm512_broadcast_f64x2 of a value from memory is VBROADCASTF64X2 in GCC, while Clang emits VBROADCASTF32X4, the AVX512F instruction with the same result; with a mask, _mm512_mask_broadcast_f64x2, both use VBROADCASTF64X2, since only it masks by quadwords. From a register, where no form of this instruction exists, both use VSHUFF64X2 with immediate 0.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2, as for VBROADCASTF32X4.

Forms

Every encoding of VBROADCASTF64X2 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VBROADCASTF64X2 ymm {k}{z}, m128 VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512EVEX.256.66.0F38.W1 1A /rAVX10.1 or AVX512DQ + AVX512VL
VBROADCASTF64X2 zmm {k}{z}, m128 VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512EVEX.512.66.0F38.W1 1A /rAVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelymm {k}{z}, m128no mask
zmm {k}{z}, m128no mask		ymm {k}{z}, m128with a mask, zeroingzmm {k}{z}, m128with a mask, zeroing
Skylake-SP, Ice Lake8 / 0.5p0158 / 0.5p0158 / 0.5p015
Sapphire Rapids8 / 0.33p2 p3 p109 / 0.33p0159 / 0.5p05
Zen 48 / 0.5FP1 FP28 / 0.5FP1 FP28 / 0.5FP1 FP2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Broadcast: 2 doubles go to every 128-bit block of the result.
VBROADCASTF64X2: one 128-bit block everywhereResult doubles 7 to 0: a1, unchanged (bit 6 of k1 is 0), a1, a0, a1, a0, a1, a0.01m128a11111110k1a0a1a0a1a0a1a1zmm1

Shown for the zmm form; the ymm form works the same on 4 doubles. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result doubles 7 to 0: a1, unchanged (bit 6 of k1 is 0), a1, a0, a1, a0, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = mem.q[i % 2]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VBROADCASTF64X2 ymm {k}{z}, m128 VBROADCASTF64X2 zmm {k}{z}, m128
ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
m128explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms
write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBROADCASTF64X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm256_mask_broadcast_f64x2 __m256d _mm256_mask_broadcast_f64x2(__m256d __O, __mmask8 __M, __m128d __A)

VBROADCASTF64X2 ymm {k}, m128 EVEX.256 -mavx512vl -mavx512dqwhen __A comes from memory

_mm256_maskz_broadcast_f64x2 __m256d _mm256_maskz_broadcast_f64x2(__mmask8 __M, __m128d __A)

VBROADCASTF64X2 ymm {k}{z}, m128 EVEX.256 -mavx512vl -mavx512dqwhen __A comes from memory

_mm512_broadcast_f64x2 __m512d _mm512_broadcast_f64x2(__m128d __A)

VBROADCASTF64X2 zmm, m128 EVEX.512 -mavx512dqwhen __A comes from memory; Clang emits the equivalent VBROADCASTF32X4

_mm512_mask_broadcast_f64x2 __m512d _mm512_mask_broadcast_f64x2(__m512d __O, __mmask8 __M, __m128d __A)

VBROADCASTF64X2 zmm {k}, m128 EVEX.512 -mavx512dqwhen __A comes from memory

_mm512_maskz_broadcast_f64x2 __m512d _mm512_maskz_broadcast_f64x2(__mmask8 __M, __m128d __A)

VBROADCASTF64X2 zmm {k}{z}, m128 EVEX.512 -mavx512dqwhen __A comes from memory

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512DQ_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512DQ_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Same as AVX512DQ_256

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-12 (VBROADCAST)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.