VBROADCASTF64X4 instruction (AVX10.1)

VBROADCASTF64X4 loads four doubles, 32 bytes, from memory and repeats them in both 256-bit halves of a ZMM register, under a mask of quadwords. It is VBROADCASTI64X4 under a floating-point name: the bits are copied, not converted, so no SIMD exception can arise, and that page covers the forms. It exists only at 512 bits, takes only a memory source and needs only AVX512F. VBROADCASTF32X8 gives the same result unmasked with a mask of singles, and VBROADCASTF64X2 repeats 16 bytes four times.

Recorded on Zen 5

The one recorded case, vbroadcastf64x4 zmm17{k5}, ymmword ptr [mem], ran with E1h in the low byte of K5: element 0 took the first double of memory, elements 5, 6 and 7 took the second, third and fourth, each from its place within the 32 bytes, and elements 1 to 4 kept their old values.

In compiled code

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_broadcast_f64x4 of a value in memory to VBROADCASTF64X4. For a value already in a YMM register, which the instruction cannot take, GCC emits VSHUFF64X2 with 44h and Clang VINSERTF64X4 of the register into its own upper half. A loop that multiplies by a repeating pattern of four doubles, g[i] = d[i] * p4[i & 3], is not vectorized by either compiler at -O2: both multiply one element at a time with VMULSD.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2, two per cycle.

Forms

Every encoding of VBROADCASTF64X4 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VBROADCASTF64X4 zmm {k}{z}, m256` VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512	`EVEX.512.66.0F38.W1 1B /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`zmm {k}{z}, m256`no mask	`zmm {k}{z}, m256`with a mask, zeroing
Skylake-SP, Ice Lake	8 / 0.5p015	8 / 0.5p015
Sapphire Rapids	8 / 0.33p2 p3 p10	9 / 0.5p05
Zen 4	8 / 0.5FP1 FP2	8 / 0.5FP1 FP2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Broadcast: 4 doubles go to every 256-bit block of the result.

The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result doubles 7 to 0: a3, unchanged (bit 6 of k1 is 0), a1, a0, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(8):
    if k1[i]:
        zmm1.q[i] = mem.q[i % 4]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VBROADCASTF64X4 zmm {k}{z}, m256`
`zmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms: write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBROADCASTF64X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm512_broadcast_f64x4` `__m512d _mm512_broadcast_f64x4(__m256d __A)`	`VBROADCASTF64X4 zmm, m256` EVEX.512 -mavx512fwhen __A comes from memory
`_mm512_mask_broadcast_f64x4` `__m512d _mm512_mask_broadcast_f64x4(__m512d __O, __mmask8 __M, __m256d __A)`	`VBROADCASTF64X4 zmm {k}, m256` EVEX.512 -mavx512fwhen __A comes from memory
`_mm512_maskz_broadcast_f64x4` `__m512d _mm512_maskz_broadcast_f64x4(__mmask8 __M, __m256d __A)`	`VBROADCASTF64X4 zmm {k}{z}, m256` EVEX.512 -mavx512fwhen __A comes from memory

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512F_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX512F_512

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

In compiled code#