VBROADCASTI32X4

VBROADCASTI32X4 loads 16 bytes from memory and repeats them in every 128-bit block of a YMM or ZMM register, writing the result under a mask of doublewords. Like VBROADCASTI128, whose page covers tables for byte shuffles, it has no register source. It needs AVX512F; VBROADCASTI64X2 is the same with a quadword mask and needs AVX512DQ.

On Zen 5, vbroadcasti32x4 zmm9{k5}, [mem] with D5E1h in the low 16 bits of K5 wrote the four doublewords of memory into doublewords 0, 5 to 8, 10, 12, 14 and 15 of ZMM9, each in its place within its block, and kept the other seven.

Uses#

• Round keys. VAES works on four AES blocks in a zmm register, so each round key must be in all four lanes; the VAESENC and VAESDEC pages show compilers loading each key with VBROADCASTI32X4.
• Tables. GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 load a 16-byte table for a 512-bit VPSHUFB lookup with VBROADCASTI32X4, from one 16-byte copy of the table.
• Rows into lanes. A mask that selects one block turns it into an insert from memory. Intel’s optimization manual transposes BF16 matrices this way: one unmasked VBROADCASTI32X4 and three masked with 0F0h, 0F00h and 0F000h place four 16-byte rows in the four blocks of a register (Section 20.16.1, Example 20-26).

The masked intrinsics _mm512_mask_broadcast_i32x4 and _mm512_maskz_broadcast_i32x4 compile to VBROADCASTI32X4 in both compilers, as does the plain one of a loaded value; of a value in a register, which the instruction cannot take, GCC makes a VSHUFI32X4. The 256-bit _mm256_broadcast_i32x4 is VBROADCASTI32X4 in GCC and VBROADCASTI128 in Clang.

AMD’s Zen 5 latency spreadsheet gives VBROADCASTI32X4 one cycle on pipe FP1 or FP2 and two per cycle, where the VEX VBROADCASTI128 row names no pipe. Zen 5’s 2 recorded cases cover both widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = mem.d[i % 4]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBROADCASTI32X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VADDSH
• VADDSS
• VAESDEC
• VAESDECLAST
• VAESENC
• VAESENCLAST
• VALIGND
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16

All 686 AVX10.1 instructions