VBROADCASTI32X8 instruction (AVX10.1)

VBROADCASTI32X8 loads 32 bytes from memory and repeats them in both 256-bit halves of a ZMM register, writing the result under a mask of doublewords. It exists only at 512 bits, has no register source, and needs AVX512DQ (or AVX10.1). Unmasked it gives the same result as VBROADCASTI64X4, which needs only AVX512F; the two differ in the element size of the mask, as VBROADCASTI32X4 and VBROADCASTI64X2 do for 16 bytes.

On Zen 5, vbroadcasti32x8 zmm5{k4}, [mem] with 6DE5h in the low 16 bits of K4 wrote doublewords 0, 2, 5 to 8, 10, 11, 13 and 14 of ZMM5, each from the doubleword of memory at the same place within its half, and kept the other six.

In compiled code

GCC 14 at -O2 with -march=x86-64-v4 compiles _mm512_broadcast_i32x8 of a loaded value to VBROADCASTI32X8 and _mm512_broadcast_i64x4 to VBROADCASTI64X4. Clang 23 emits VBROADCASTI64X4 for both and keeps VBROADCASTI32X8 for the masked _mm512_mask_broadcast_i32x8, which GCC also compiles to it. Of a value already in a register, the broadcast becomes a shuffle or an insert: GCC uses VSHUFI32X4 with immediate 44h, Clang VINSERTF64X4 of the register into itself.

AMD’s Zen 5 latency spreadsheet gives VBROADCASTI32X8 one cycle on pipe FP1 or FP2 and two per cycle, the same as VBROADCASTI64X4. Zen 5’s recorded case covers the only form, masked.

Forms

Every encoding of VBROADCASTI32X8 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VBROADCASTI32X8 zmm {k}{z}, m256` VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512	`EVEX.512.66.0F38.W0 5B /r`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`zmm {k}{z}, m256`no mask	`zmm {k}{z}, m256`with a mask, zeroing
Skylake-SP, Ice Lake	8 / 0.5p015	8 / 0.5p015
Sapphire Rapids	8 / 0.33p2 p3 p10	9 / 0.5p05
Zen 4	8 / 0.5FP1 FP2	8 / 0.5FP1 FP2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Broadcast: 8 doublewords go to every 256-bit block of the result.

The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result doublewords 15 to 0: a7, unchanged (bit 14 of k1 is 0), a5, a4, a3, a2, a1, a0, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(16):
    if k1[i]:
        zmm1.d[i] = mem.d[i % 8]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VBROADCASTI32X8 zmm {k}{z}, m256`
`zmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms: write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBROADCASTI32X8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm512_broadcast_i32x8` `__m512i _mm512_broadcast_i32x8(__m256i __A)`	`VBROADCASTI32X8 zmm, m256` EVEX.512 -mavx512dqwhen __A comes from memory; Clang emits the equivalent VBROADCASTI64X4
`_mm512_mask_broadcast_i32x8` `__m512i _mm512_mask_broadcast_i32x8(__m512i __O, __mmask16 __M, __m256i __A)`	`VBROADCASTI32X8 zmm {k}, m256` EVEX.512 -mavx512dqwhen __A comes from memory
`_mm512_maskz_broadcast_i32x8` `__m512i _mm512_maskz_broadcast_i32x8(__mmask16 __M, __m256i __A)`	`VBROADCASTI32X8 zmm {k}{z}, m256` EVEX.512 -mavx512dqwhen __A comes from memory

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX512DQ_512

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

In compiled code#