x86-64.net

Instruction

VBROADCASTSD

Copies one double from memory or an XMM register to every element of a vector.

Extensions
Forms
6 (2 VEX, 4 EVEX)
Data
Intel XED v2026.08.23

VBROADCASTSD copies one double to every element of a ymm or zmm register. It is VBROADCASTSS for 64-bit elements, and its sources grow the same way: AVX reads only a 64-bit value in memory, AVX2 adds the low double of an xmm register, and AVX-512F adds zmm destinations and a write mask.

No xmm form

Unlike the single-precision broadcast, it has no 128-bit form: Intel’s manual makes VEX.L = 0 an invalid opcode, and the EVEX encoding needs 256 or 512 bits too. Two doubles in an xmm register are what VMOVDDUP gives, and GCC 14 and Clang 23 at -O2 compile _mm_set1_pd(x) to vmovddup xmm0, xmm0. In EVEX, the same opcode with W0 instead of W1 is VBROADCASTF32X2, which repeats a pair of singles.

Register or memory

_mm256_set1_pd(x) with x in a register shows what AVX2 added. With -mavx, both compilers emit VMOVDDUP and then VINSERTF128 to copy the low half up; with -march=x86-64-v3, one vbroadcastsd ymm0, xmm0. A value in memory needs only AVX: _mm256_set1_pd(*p) is vbroadcastsd ymm0, qword ptr [rdi] for both targets. Loops over doubles load their constants this way, from an 8-byte literal: the -0.0 that flips signs in a negation, or the 1.0 of 1.0 - b[i].

Under a mask

The masked cases recorded on Zen 5 show that the mask picks doubles: vbroadcastsd zmm9{k4}, qword ptr [mem], with k4 selecting elements 0, 2 and 5 to 7, wrote the value there and left the other three as zmm9 held them, and vbroadcastsd ymm0{k5}{z}, xmm31, with only element 0 selected, gave the value once and zeros above it.

AMD’s Zen 5 guide lists VBROADCASTSD like the 256-bit VBROADCASTSS: one macro-op on the pipes FP1 and FP2, with a latency of 1 cycle. VBROADCASTF128 and VBROADCASTF64X2 repeat 16 bytes instead, and VPBROADCASTQ is the integer form.

In the optimization guide

What the optimization guide says about VBROADCASTSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

  • Vectors and AVX2: A 256-bit broadcast is cheapest from memory: one operation, a cycle on top of the load.

Skylake to Cooper Lake

  • AVX-512 and frequency on the servers: A broadcast of a 32-bit or 64-bit element from memory runs on the load ports, sparing port 5; a 16-bit one still goes through port 5, so it gains nothing from the memory form.

Forms

Every encoding of VBROADCASTSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VBROADCASTSD ymm, m64 VBROADCASTSD_YMMqq_MEMqVEX.256.66.0F38.W0 19 /rAVX
VBROADCASTSD ymm, xmm VBROADCASTSD_YMMqq_XMMdqVEX.256.66.0F38.W0 19 /rAVX2
VBROADCASTSD zmm {k}{z}, m64 VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512EVEX.512.66.0F38.W1 19 /rAVX10.1 or AVX512F
VBROADCASTSD zmm {k}{z}, xmm VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512EVEX.512.66.0F38.W1 19 /rAVX10.1 or AVX512F
VBROADCASTSD ymm {k}{z}, m64 VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512EVEX.256.66.0F38.W1 19 /rAVX10.1 or AVX512F + AVX512VL
VBROADCASTSD ymm {k}{z}, xmm VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512EVEX.256.66.0F38.W1 19 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelymm, m64ymm, xmm
zmm {k}{z}, xmm
ymm {k}{z}, xmm		zmm {k}{z}, m64no mask
ymm {k}{z}, m64no mask		zmm {k}{z}, m64with a mask, zeroingymm {k}{z}, m64with a mask, zeroing
Sandy Bridge7 / 1p5
Haswell, Skylake7 / 0.5p233 / 1p5
Broadwell6 / 0.5p233 / 1p5
Skylake-SP, Ice Lake7 / 0.5p233 / 1p58 / 0.5p0158 / 0.5p0158 / 0.5p015
Alder Lake8 / 0.33p2 p3 p103 / 1p5
Sapphire Rapids8 / 0.33p2 p3 p103 / 1p58 / 0.33p2 p3 p109 / 0.5p059 / 0.33p015
Lunar Lake7 / 2.33p20 p21 p223 / 0.5V2 V3
Piledriver6 / 2FPFMA FPU0 FPU1
Zen8 / 0.5FPU1 FPU22 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU22 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP22 / 1FP1
Zen 48 / 0.5FP1 FP22 / 11FP19 / 1FP19 / 1FP19 / 1FP1
Jaguar6 / 2FPA FPM FPU0 FPU1
  1. Zen 4 model: AMD's spreadsheets give latency 1 for Zen 4 and Zen 5 (AMD 57647, row 924; AMD 58455, row 1297).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Broadcast: the low double goes to every double of the result.
VBROADCASTSD: one double everywhereResult doubles 7 to 0: a0, unchanged (bit 6 of k1 is 0), a0, a0, a0, a0, a0, a0.01xmm2or m64a11111110k1a0a0a0a0a0a0a0zmm1

Shown for the zmm form; the ymm form works the same on 4 doubles. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result doubles 7 to 0: a0, unchanged (bit 6 of k1 is 0), a0, a0, a0, a0, a0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = src2.q[0]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VBROADCASTSD ymm, xmm/m64
ymmexplicitwrite
xmm/m64explicitread
VBROADCASTSD ymm {k}{z}, xmm/m64 VBROADCASTSD zmm {k}{z}, xmm/m64
ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m64explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-6
EVEX forms
AVX512-E6

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBROADCASTSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm256_broadcast_f32x2 __m256 _mm256_broadcast_f32x2(__m128 __A)

VBROADCASTSD ymm, xmm VEX.256 -mavx512vl -mavx512dq

_mm256_broadcast_sd __m256d _mm256_broadcast_sd(const double *__a)

VBROADCASTSD ymm, m64 VEX.256 -mavx

_mm256_broadcastsd_pd __m256d _mm256_broadcastsd_pd(__m128d __X)

VBROADCASTSD ymm, xmm VEX.256 -mavx2

_mm256_mask_broadcastsd_pd __m256d _mm256_mask_broadcastsd_pd(__m256d __O, __mmask8 __M, __m128d __A)

VBROADCASTSD ymm {k}, xmm EVEX.256 -mavx512vl

_mm256_maskz_broadcastsd_pd __m256d _mm256_maskz_broadcastsd_pd(__mmask8 __M, __m128d __A)

VBROADCASTSD ymm {k}{z}, xmm EVEX.256 -mavx512vl

_mm512_broadcastsd_pd __m512d _mm512_broadcastsd_pd(__m128d __A)

VBROADCASTSD zmm, xmm EVEX.512 -mavx512f

_mm512_set1_pd __m512d _mm512_set1_pd(double __w)

VBROADCASTSD zmm, xmm EVEX.512 -mavx512f

_mm512_mask_broadcastsd_pd __m512d _mm512_mask_broadcastsd_pd(__m512d __O, __mmask8 __M, __m128d __A)

VBROADCASTSD zmm {k}, xmm EVEX.512 -mavx512f

_mm512_maskz_broadcastsd_pd __m512d _mm512_maskz_broadcastsd_pd(__mmask8 __M, __m128d __A)

VBROADCASTSD zmm {k}{z}, xmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-12 (VBROADCAST)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.