x86-64.net

Instruction

VBROADCASTSD

Copies one double from memory or an XMM register to every element of a vector.

Extensions
Forms
6 (2 VEX, 4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VBROADCASTSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VBROADCASTSD ymm, m64 VBROADCASTSD_YMMqq_MEMqVEX.256.66.0F38.W0 19 /rAVX
VBROADCASTSD ymm, xmm VBROADCASTSD_YMMqq_XMMdqVEX.256.66.0F38.W0 19 /rAVX2
VBROADCASTSD zmm {k}{z}, m64 VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512EVEX.512.66.0F38.W1 19 /rAVX10.1 or AVX512F
VBROADCASTSD zmm {k}{z}, xmm VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512EVEX.512.66.0F38.W1 19 /rAVX10.1 or AVX512F
VBROADCASTSD ymm {k}{z}, m64 VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512EVEX.256.66.0F38.W1 19 /rAVX10.1 or AVX512F + AVX512VL
VBROADCASTSD ymm {k}{z}, xmm VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512EVEX.256.66.0F38.W1 19 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBROADCASTSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm256_broadcast_f32x2 __m256 _mm256_broadcast_f32x2(__m128 __A)

VBROADCASTSD ymm, xmm VEX.256 -mavx512vl -mavx512dq

_mm256_broadcast_sd __m256d _mm256_broadcast_sd(const double *__a)

VBROADCASTSD ymm, m64 VEX.256 -mavx

_mm256_broadcastsd_pd __m256d _mm256_broadcastsd_pd(__m128d __X)

VBROADCASTSD ymm, xmm VEX.256 -mavx2

_mm256_mask_broadcastsd_pd __m256d _mm256_mask_broadcastsd_pd(__m256d __O, __mmask8 __M, __m128d __A)

VBROADCASTSD ymm {k}, xmm EVEX.256 -mavx512vl

_mm256_maskz_broadcastsd_pd __m256d _mm256_maskz_broadcastsd_pd(__mmask8 __M, __m128d __A)

VBROADCASTSD ymm {k}{z}, xmm EVEX.256 -mavx512vl

_mm512_broadcastsd_pd __m512d _mm512_broadcastsd_pd(__m128d __A)

VBROADCASTSD zmm, xmm EVEX.512 -mavx512f

_mm512_set1_pd __m512d _mm512_set1_pd(double __w)

VBROADCASTSD zmm, xmm EVEX.512 -mavx512f

_mm512_mask_broadcastsd_pd __m512d _mm512_mask_broadcastsd_pd(__m512d __O, __mmask8 __M, __m128d __A)

VBROADCASTSD zmm {k}, xmm EVEX.512 -mavx512f

_mm512_maskz_broadcastsd_pd __m512d _mm512_maskz_broadcastsd_pd(__mmask8 __M, __m128d __A)

VBROADCASTSD zmm {k}{z}, xmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.