x86-64.net

Instruction

VBROADCASTSS

Copies one single from memory or an XMM register to every element of a vector.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VBROADCASTSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VBROADCASTSS xmm, m32 VBROADCASTSS_XMMdq_MEMdVEX.128.66.0F38.W0 18 /rAVX
VBROADCASTSS ymm, m32 VBROADCASTSS_YMMqq_MEMdVEX.256.66.0F38.W0 18 /rAVX
VBROADCASTSS xmm, xmm VBROADCASTSS_XMMdq_XMMdqVEX.128.66.0F38.W0 18 /rAVX2
VBROADCASTSS ymm, xmm VBROADCASTSS_YMMqq_XMMdqVEX.256.66.0F38.W0 18 /rAVX2
VBROADCASTSS zmm {k}{z}, m32 VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512EVEX.512.66.0F38.W0 18 /rAVX10.1 or AVX512F
VBROADCASTSS zmm {k}{z}, xmm VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512EVEX.512.66.0F38.W0 18 /rAVX10.1 or AVX512F
VBROADCASTSS xmm {k}{z}, m32 VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512EVEX.128.66.0F38.W0 18 /rAVX10.1 or AVX512F + AVX512VL
VBROADCASTSS xmm {k}{z}, xmm VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512EVEX.128.66.0F38.W0 18 /rAVX10.1 or AVX512F + AVX512VL
VBROADCASTSS ymm {k}{z}, m32 VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512EVEX.256.66.0F38.W0 18 /rAVX10.1 or AVX512F + AVX512VL
VBROADCASTSS ymm {k}{z}, xmm VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512EVEX.256.66.0F38.W0 18 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VBROADCASTSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_broadcast_ss __m128 _mm_broadcast_ss(const float *__a)

VBROADCASTSS xmm, m32 VEX.128 -mavx

_mm_broadcastss_ps __m128 _mm_broadcastss_ps(__m128 __X)

VBROADCASTSS xmm, xmm VEX.128 -mavx2

_mm_load_ps1 __m128 _mm_load_ps1(const float *p)

VBROADCASTSS xmm, m32 VEX.128 -mavxwith AVX enabled

_mm_set1_pch __m128h _mm_set1_pch(_Complex _Float16 h)

VBROADCASTSS xmm, xmm VEX.128 -mavx512fp16 -mavx512vl

_mm_mask_broadcastss_ps __m128 _mm_mask_broadcastss_ps(__m128 __O, __mmask8 __M, __m128 __A)

VBROADCASTSS xmm {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_broadcastss_ps __m128 _mm_maskz_broadcastss_ps(__mmask8 __M, __m128 __A)

VBROADCASTSS xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_broadcast_ss __m256 _mm256_broadcast_ss(const float *__a)

VBROADCASTSS ymm, m32 VEX.256 -mavx

_mm256_broadcastss_ps __m256 _mm256_broadcastss_ps(__m128 __X)

VBROADCASTSS ymm, xmm VEX.256 -mavx2

_mm256_set1_pch __m256h _mm256_set1_pch(_Complex _Float16 h)

VBROADCASTSS ymm, xmm VEX.256 -mavx512fp16 -mavx512vl

_mm256_mask_broadcastss_ps __m256 _mm256_mask_broadcastss_ps(__m256 __O, __mmask8 __M, __m128 __A)

VBROADCASTSS ymm {k}, xmm EVEX.256 -mavx512vl

_mm256_maskz_broadcastss_ps __m256 _mm256_maskz_broadcastss_ps(__mmask8 __M, __m128 __A)

VBROADCASTSS ymm {k}{z}, xmm EVEX.256 -mavx512vl

_mm512_broadcastss_ps __m512 _mm512_broadcastss_ps(__m128 __A)

VBROADCASTSS zmm, xmm EVEX.512 -mavx512f

_mm512_set1_pch __m512h _mm512_set1_pch(_Complex _Float16 __h)

VBROADCASTSS zmm, xmm EVEX.512 -mavx512fp16

_mm512_set1_ps __m512 _mm512_set1_ps(float __w)

VBROADCASTSS zmm, xmm EVEX.512 -mavx512f

_mm512_mask_broadcastss_ps __m512 _mm512_mask_broadcastss_ps(__m512 __O, __mmask16 __M, __m128 __A)

VBROADCASTSS zmm {k}, xmm EVEX.512 -mavx512f

_mm512_maskz_broadcastss_ps __m512 _mm512_maskz_broadcastss_ps(__mmask16 __M, __m128 __A)

VBROADCASTSS zmm {k}{z}, xmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.