VCMPBF16

VCMPBF16 compares bfloat16 values element by element under one of the 32 predicates of VCMPPS, chosen by bits 4:0 of the immediate, and writes one bit per element to a mask register, up to 32 for zmm registers; elements that its write mask leaves out get 0. Like VCMPPH it exists only in EVEX form with a mask destination, and it takes a source broadcast from 16 bits of memory but no {sae}. It belongs to AVX10.2, and its opcode is C2h in map 0F3A with the F2 prefix and W0, where VCMPPH has no prefix.

Signaling predicates that cannot signal#

VCMPPS’s page explains that bit 4 of the predicate decides whether a quiet NaN raises the invalid-operation exception. The AVX10.2 specification (revision 7.0) keeps the full table of 32 predicates, but VCMPBF16 raises no exceptions and leaves MXCSR alone, so a predicate and its partner 16 apart, LT_OS (1) and LT_OQ (17) for instance, give the same mask. It also reads denormals as zeros, so a denormal compares equal to zero and to every other denormal, of either sign. VADDBF16’s page covers these fixed rules.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 vectorizes compares over global __bf16 arrays with VCMPBF16 on zmm registers, the second operand from memory: M[i] = X[i] < Y[i] uses predicate 1 and turns the mask into words of 0 or 1 with VPMOVM2W and a VPSRLW by 15, and Z[i] = X[i] == Y[i] ? Z[i] : X[i] uses predicate 0 and a masked VMOVDQU16. isnan(X[i]) is predicate 3, unordered, of each vector with itself, and _mm512_cmp_pbh_mask(a, b, _CMP_LT_OQ) gives the instruction directly. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    a = zmm2.bf16[i]
    b = src3.bf16[i]
    k1[i] = k2[i] and fcmp(imm8, a, b)
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# m16bcst: src3.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; denormal inputs read as zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VADDBF16
• VCOMISBF16
• VCOMXSD
• VCOMXSH
• VCOMXSS
• VCVT2PH2BF8
• VCVT2PH2BF8S
• VCVT2PH2HF8
• VCVT2PH2HF8S
• VCVT2PS2PHX
• VCVTBF162IBS
• VCVTBF162IUBS
• VCVTBIASPH2BF8
• VCVTBIASPH2BF8S
• VCVTBIASPH2HF8
• VCVTBIASPH2HF8S
• VCVTHF82PH
• VCVTPH2BF8
• VCVTPH2BF8S
• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS

All 96 AVX10.2 instructions