x86-64.net

Instruction

VCMPPD

Compares packed doubles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCMPPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCMPPD xmm, xmm, m128, imm8 VCMPPD_XMMdq_XMMdq_MEMdq_IMMbVEX.128.66.0F.WIG C2 /r ibAVX
VCMPPD xmm, xmm, xmm, imm8 VCMPPD_XMMdq_XMMdq_XMMdq_IMMbVEX.128.66.0F.WIG C2 /r ibAVX
VCMPPD ymm, ymm, m256, imm8 VCMPPD_YMMqq_YMMqq_MEMqq_IMMbVEX.256.66.0F.WIG C2 /r ibAVX
VCMPPD ymm, ymm, ymm, imm8 VCMPPD_YMMqq_YMMqq_YMMqq_IMMbVEX.256.66.0F.WIG C2 /r ibAVX
VCMPPD k {k}, zmm, zmm, imm8, {sae} VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512EVEX.512.66.0F.W1 C2 /r ibAVX10.1 or AVX512F
VCMPPD k {k}, zmm, m512/m64bcst, imm8 VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512EVEX.512.66.0F.W1 C2 /r ibAVX10.1 or AVX512F
VCMPPD k {k}, xmm, xmm, imm8 VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512EVEX.128.66.0F.W1 C2 /r ibAVX10.1 or AVX512F + AVX512VL
VCMPPD k {k}, xmm, m128/m64bcst, imm8 VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512EVEX.128.66.0F.W1 C2 /r ibAVX10.1 or AVX512F + AVX512VL
VCMPPD k {k}, ymm, ymm, imm8 VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512EVEX.256.66.0F.W1 C2 /r ibAVX10.1 or AVX512F + AVX512VL
VCMPPD k {k}, ymm, m256/m64bcst, imm8 VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512EVEX.256.66.0F.W1 C2 /r ibAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cmp_pd_mask __mmask8 _mm_cmp_pd_mask(__m128d a, __m128d b, const int p)

VCMPPD k, xmm, xmm, imm8 EVEX.128 -mavx512vl

_mm_cmpeq_pd __m128d _mm_cmpeq_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpge_pd __m128d _mm_cmpge_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpgt_pd __m128d _mm_cmpgt_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmple_pd __m128d _mm_cmple_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmplt_pd __m128d _mm_cmplt_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpneq_pd __m128d _mm_cmpneq_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpnge_pd __m128d _mm_cmpnge_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpngt_pd __m128d _mm_cmpngt_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpnle_pd __m128d _mm_cmpnle_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpnlt_pd __m128d _mm_cmpnlt_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpord_pd __m128d _mm_cmpord_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpunord_pd __m128d _mm_cmpunord_pd(__m128d __a, __m128d __b)

VCMPPD xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_mask_cmp_pd_mask __mmask8 _mm_mask_cmp_pd_mask(__mmask8 m, __m128d a, __m128d b, const int p)

VCMPPD k {k}, xmm, xmm, imm8 EVEX.128 -mavx512vl

_mm256_cmp_pd __m256d _mm256_cmp_pd(__m256d a, __m256d b, const int c)

VCMPPD ymm, ymm, ymm, imm8 VEX.256 -mavx

_mm256_cmp_pd_mask __mmask8 _mm256_cmp_pd_mask(__m256d a, __m256d b, const int p)

VCMPPD k, ymm, ymm, imm8 EVEX.256 -mavx512vl

_mm256_mask_cmp_pd_mask __mmask8 _mm256_mask_cmp_pd_mask(__mmask8 m, __m256d a, __m256d b, const int p)

VCMPPD k {k}, ymm, ymm, imm8 EVEX.256 -mavx512vl

_mm512_cmp_pd_mask __mmask8 _mm512_cmp_pd_mask(__m512d A, __m512d B, const int P)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmp_pd_mask __mmask8 _mm512_mask_cmp_pd_mask(__mmask8 U, __m512d A, __m512d B, const int P)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmp_round_pd_mask __mmask8 _mm512_cmp_round_pd_mask(__m512d A, __m512d B, const int P, const int R)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmp_round_pd_mask __mmask8 _mm512_mask_cmp_round_pd_mask(__mmask8 U, __m512d A, __m512d B, const int P, const int R)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpeq_pd_mask __mmask8 _mm512_cmpeq_pd_mask(__m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpeq_pd_mask __mmask8 _mm512_mask_cmpeq_pd_mask(__mmask8 k, __m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmple_pd_mask __mmask8 _mm512_cmple_pd_mask(__m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmple_pd_mask __mmask8 _mm512_mask_cmple_pd_mask(__mmask8 k, __m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmplt_pd_mask __mmask8 _mm512_cmplt_pd_mask(__m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmplt_pd_mask __mmask8 _mm512_mask_cmplt_pd_mask(__mmask8 k, __m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpneq_pd_mask __mmask8 _mm512_cmpneq_pd_mask(__m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpneq_pd_mask __mmask8 _mm512_mask_cmpneq_pd_mask(__mmask8 k, __m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpnle_pd_mask __mmask8 _mm512_cmpnle_pd_mask(__m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpnle_pd_mask __mmask8 _mm512_mask_cmpnle_pd_mask(__mmask8 k, __m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpnlt_pd_mask __mmask8 _mm512_cmpnlt_pd_mask(__m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpnlt_pd_mask __mmask8 _mm512_mask_cmpnlt_pd_mask(__mmask8 k, __m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpord_pd_mask __mmask8 _mm512_cmpord_pd_mask(__m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpord_pd_mask __mmask8 _mm512_mask_cmpord_pd_mask(__mmask8 k, __m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpunord_pd_mask __mmask8 _mm512_cmpunord_pd_mask(__m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpunord_pd_mask __mmask8 _mm512_mask_cmpunord_pd_mask(__mmask8 k, __m512d A, __m512d B)

VCMPPD k, zmm, zmm, imm8 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.