VCMPPD

VCMPPD compares doubles element by element, two in an XMM register, four in a YMM and eight in a ZMM one, under the same 32 predicates as VCMPPS, whose page describes how bits 3 and 4 of the immediate change the treatment of NaNs and what Zen 5 did with them. The VEX forms write all ones or zero to each quadword, as SSE2’s CMPPD does with its eight predicates; the EVEX forms write at most eight bits to a mask register and clear the rest, so the byte-sized mask instructions of AVX512DQ, such as KTESTB and KMOVB, cover the result.

Two cases recorded on Zen 5 show details that hold for both widths:

• Under a write mask the always-true predicate copies the mask: vcmppd k2{k1}, zmm17, zmm30, {sae}, 0xf gave A0h, the low byte of K1.
• vcmppd ymm12, ymm6, ymm6, 0x16, not less or equal and quiet, came out false in every element but set MXCSR’s denormal flag, DE, for a denormal input, as DAZ was clear.

From doubles to int results#

A compare of doubles gives 64-bit elements, which C code usually wants as ints. For r[i] = isnan(a[i]), GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 compare each vector with itself with predicate 3, unordered, and AND the result with ones, then narrow the quadwords: Clang with VEXTRACTF128 and VPACKSSDW, GCC with two VPERM2I128, two VPSHUFD and a VPUNPCKLQDQ. With -march=x86-64-v4 the compare writes a mask register, one bit per element whatever the width: Clang turns it straight into doublewords with VPMOVM2D and shifts each right by 31, while GCC writes quadword ones under the mask with a zero-masked VMOVDQA64 and still narrows, with one VPERMT2D per two vectors.

AMD’s latency spreadsheet for Zen 5 lists VCMPPD as it lists VCMPPS: 2 cycles for the VEX forms, and 3, 4 and 6 cycles for XMM, YMM and ZMM sources when the result goes to a mask register.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    a = ymm2.f64[i]
    b = src3.f64[i]
    if fcmp(imm8, a, b):
        ymm1.q[i] = -1
    else:
        ymm1.q[i] = 0
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# ymm1 is zeroed from bit VL up

for i in range(VL // 64):
    a = zmm2.f64[i]
    b = src3.f64[i]
    k1[i] = k2[i] and fcmp(imm8, a, b)
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# m64bcst: src3.f64[i] is the m64 for every i
# {sae}: no exception flags
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPD
• VADDPS
• VADDSD
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS

All 253 AVX instructions

More AVX10.1 instructions

• VALIGND
• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ

All 686 AVX10.1 instructions