x86-64.net

Instruction

VCMPPH

Compares packed half-precision values with one of 32 predicates chosen by an immediate and writes the results to a mask register.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCMPPH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCMPPH k {k}, xmm, xmm, imm8 VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512EVEX.128.NP.0F3A.W0 C2 /r ibAVX10.1 or AVX512_FP16 + AVX512VL
VCMPPH k {k}, xmm, m128/m16bcst, imm8 VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512EVEX.128.NP.0F3A.W0 C2 /r ibAVX10.1 or AVX512_FP16 + AVX512VL
VCMPPH k {k}, ymm, ymm, imm8 VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512EVEX.256.NP.0F3A.W0 C2 /r ibAVX10.1 or AVX512_FP16 + AVX512VL
VCMPPH k {k}, ymm, m256/m16bcst, imm8 VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512EVEX.256.NP.0F3A.W0 C2 /r ibAVX10.1 or AVX512_FP16 + AVX512VL
VCMPPH k {k}, zmm, zmm, imm8, {sae} VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512EVEX.512.NP.0F3A.W0 C2 /r ibAVX10.1 or AVX512_FP16
VCMPPH k {k}, zmm, m512/m16bcst, imm8 VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512EVEX.512.NP.0F3A.W0 C2 /r ibAVX10.1 or AVX512_FP16

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cmp_ph_mask __mmask8 _mm_cmp_ph_mask(__m128h a, __m128h b, const int p)

VCMPPH k, xmm, xmm, imm8 EVEX.128 -mavx512fp16 -mavx512vl

_mm_mask_cmp_ph_mask __mmask8 _mm_mask_cmp_ph_mask(__mmask8 m, __m128h a, __m128h b, const int p)

VCMPPH k, xmm, xmm, imm8 EVEX.128 -mavx512fp16 -mavx512vl

_mm256_cmp_ph_mask __mmask16 _mm256_cmp_ph_mask(__m256h a, __m256h b, const int p)

VCMPPH k, ymm, ymm, imm8 EVEX.256 -mavx512fp16 -mavx512vl

_mm256_mask_cmp_ph_mask __mmask16 _mm256_mask_cmp_ph_mask(__mmask16 m, __m256h a, __m256h b, const int p)

VCMPPH k, ymm, ymm, imm8 EVEX.256 -mavx512fp16 -mavx512vl

_mm512_cmp_ph_mask __mmask32 _mm512_cmp_ph_mask(__m512h A, __m512h B, const int P)

VCMPPH k, zmm, zmm, imm8 EVEX.512 -mavx512fp16

_mm512_mask_cmp_ph_mask __mmask32 _mm512_mask_cmp_ph_mask(__mmask32 U, __m512h A, __m512h B, const int P)

VCMPPH k, zmm, zmm, imm8 EVEX.512 -mavx512fp16

_mm512_cmp_round_ph_mask __mmask32 _mm512_cmp_round_ph_mask(__m512h A, __m512h B, const int P, const int R)

VCMPPH k, zmm, zmm, imm8 EVEX.512 -mavx512fp16

_mm512_mask_cmp_round_ph_mask __mmask32 _mm512_mask_cmp_round_ph_mask(__mmask32 U, __m512h A, __m512h B, const int P, const int R)

VCMPPH k, zmm, zmm, imm8 EVEX.512 -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP16_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.