VCMPPH

VCMPPH compares halves element by element under one of the 32 predicates of VCMPPS, chosen by bits 4:0 of the immediate, and writes one bit per element to a mask register, up to 32 for zmm registers; elements that its write mask leaves out get 0. That page explains what bits 3 and 4 of the predicate do with NaNs. There is no vector-result form: unlike VCMPPS, which also has VEX forms writing all ones to an element, VCMPPH exists only in EVEX and only with a mask destination. It takes a source broadcast from one half and {sae} on the 512-bit register form, and reports invalid and denormal, never reading a denormal as zero since FP16 ignores DAZ (Intel’s optimization manual, Section 18.5.4). VADDPH covers the format and the CPUID bits; VCMPSH compares the low halves.

In the 0F3A map#

VCMPPS is opcode C2h in map 0F. VCMPPH is C2h with no prefix in map 0F3A, the map of FP16’s other instructions with an immediate, as VGETMANTPH’s page notes.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 vectorize compares over global _Float16 arrays with VCMPPH, GCC on zmm and Clang mostly on ymm registers, the second operand read from memory. c[i] = a[i] < b[i] ? a[i] : 0 becomes predicate 1, less than and signaling, followed by a zero-masked VMOVDQU16 that keeps the selected halves. A mask stored as 16-bit integers, m[i] = a[i] == b[i], uses predicate 0, which GCC turns into ones with a zero-masked move of a vector of 1s and Clang into all-ones words with VPMOVM2W. isnan(a[i]) is predicate 3, unordered, of each vector with itself. Counting a[i] >= 1 swaps the operands to compare 1 <= a[i] with predicate 2, before the bits are widened and added. Intel’s optimization manual shows the same instruction through _mm512_cmp_ph_mask, and notes that comparing as 16-bit integers costs the same (Sections 18.4.4 and 18.6.3).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCMPPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    a = zmm2.f16[i]
    b = src3.f16[i]
    k1[i] = k2[i] and fcmp(imm8, a, b)
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# m16bcst: src3.f16[i] is the m16 for every i
# {sae}: no exception flags
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VALIGNQ
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ

All 686 AVX10.1 instructions