VCMPPS

VCMPPS compares singles element by element under a predicate chosen by bits 4:0 of the immediate. The VEX forms write all ones or zero to each element of a vector, as SSE’s CMPPS does, which reads only bits 2:0; the EVEX forms write one bit per element to a mask register, cleared for the elements the write mask leaves out.

Thirty-two predicates#

Bits 2:0 pick one of the eight relations of CMPPS’s table. The two bits AVX added change only what a NaN does:

• Bit 3 inverts the result for unordered inputs and keeps it for ordered ones. Equal (0) becomes equal or unordered (8h), not less (5) becomes greater or equal (0Dh), and unordered (3) and ordered (7) become always false (0Bh) and always true (0Fh).
• Bit 4 inverts whether a quiet NaN raises the invalid-operation exception: equal (0) is quiet and 10h signals, less (1) signals and 11h is quiet. A signaling NaN raises it under every predicate. COMISS explains which C operators should signal.

NaNs on Zen 5#

• vcmpps ymm12, ymm6, ymm6, 0x4, not equal and quiet, gave all ones for the one quiet NaN of YMM6 and left MXCSR alone. vcmpps k3, zmm1, zmm2, 0x10, equal and signaling, set MXCSR.IE for a quiet NaN.
• With IE unmasked, vcmpps ymm0, ymm13, ymm9, 0xb, always false, raised #XM for a signaling NaN.
• A write mask masks the exceptions too: vcmpps k7{k3}, zmm0, zmm31, 0x1b had signaling NaNs only in elements K3 leaves out, and finished with IE unmasked and no flag set. With {sae}, vcmpps k7, zmm7, zmm12, {sae}, 0xd set nothing for a signaling NaN with every exception unmasked.

In compiled code#

In loops over floats, GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 pick the predicates that baseline code uses with CMPPS, none above 7. For isless, which C defines as quiet, both vectorized loops still used signaling predicates: Clang 1, and GCC 5 with the result inverted by VPANDN. With exceptions masked, as by default, the only trace is MXCSR.IE.

AMD’s latency spreadsheet for Zen 5 gives the VEX forms 2 cycles, and the forms that write a mask register 3, 4 and 6 cycles for XMM, YMM and ZMM sources.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = ymm2.f32[i]
    b = src3.f32[i]
    if fcmp(imm8, a, b):
        ymm1.d[i] = -1
    else:
        ymm1.d[i] = 0
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# ymm1 is zeroed from bit VL up

for i in range(VL // 32):
    a = zmm2.f32[i]
    b = src3.f32[i]
    k1[i] = k2[i] and fcmp(imm8, a, b)
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# m32bcst: src3.f32[i] is the m32 for every i
# {sae}: no exception flags
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPD
• VADDPS
• VADDSD
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS

All 253 AVX instructions

More AVX10.1 instructions

• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ

All 686 AVX10.1 instructions