x86-64.net

Instruction

VCMPPS

Compares packed singles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCMPPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCMPPS xmm, xmm, m128, imm8 VCMPPS_XMMdq_XMMdq_MEMdq_IMMbVEX.128.NP.0F.WIG C2 /r ibAVX
VCMPPS xmm, xmm, xmm, imm8 VCMPPS_XMMdq_XMMdq_XMMdq_IMMbVEX.128.NP.0F.WIG C2 /r ibAVX
VCMPPS ymm, ymm, m256, imm8 VCMPPS_YMMqq_YMMqq_MEMqq_IMMbVEX.256.NP.0F.WIG C2 /r ibAVX
VCMPPS ymm, ymm, ymm, imm8 VCMPPS_YMMqq_YMMqq_YMMqq_IMMbVEX.256.NP.0F.WIG C2 /r ibAVX
VCMPPS k {k}, zmm, zmm, imm8, {sae} VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512EVEX.512.NP.0F.W0 C2 /r ibAVX10.1 or AVX512F
VCMPPS k {k}, zmm, m512/m32bcst, imm8 VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512EVEX.512.NP.0F.W0 C2 /r ibAVX10.1 or AVX512F
VCMPPS k {k}, xmm, xmm, imm8 VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512EVEX.128.NP.0F.W0 C2 /r ibAVX10.1 or AVX512F + AVX512VL
VCMPPS k {k}, xmm, m128/m32bcst, imm8 VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512EVEX.128.NP.0F.W0 C2 /r ibAVX10.1 or AVX512F + AVX512VL
VCMPPS k {k}, ymm, ymm, imm8 VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512EVEX.256.NP.0F.W0 C2 /r ibAVX10.1 or AVX512F + AVX512VL
VCMPPS k {k}, ymm, m256/m32bcst, imm8 VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512EVEX.256.NP.0F.W0 C2 /r ibAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cmp_ps_mask __mmask8 _mm_cmp_ps_mask(__m128 a, __m128 b, const int p)

VCMPPS k, xmm, xmm, imm8 EVEX.128 -mavx512vl

_mm_cmpeq_ps __m128 _mm_cmpeq_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpge_ps __m128 _mm_cmpge_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpgt_ps __m128 _mm_cmpgt_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmple_ps __m128 _mm_cmple_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmplt_ps __m128 _mm_cmplt_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpneq_ps __m128 _mm_cmpneq_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpnge_ps __m128 _mm_cmpnge_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpngt_ps __m128 _mm_cmpngt_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpnle_ps __m128 _mm_cmpnle_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpnlt_ps __m128 _mm_cmpnlt_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpord_ps __m128 _mm_cmpord_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_cmpunord_ps __m128 _mm_cmpunord_ps(__m128 __a, __m128 __b)

VCMPPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_mask_cmp_ps_mask __mmask8 _mm_mask_cmp_ps_mask(__mmask8 m, __m128 a, __m128 b, const int p)

VCMPPS k {k}, xmm, xmm, imm8 EVEX.128 -mavx512vl

_mm256_cmp_ps __m256 _mm256_cmp_ps(__m256 a, __m256 b, const int c)

VCMPPS ymm, ymm, ymm, imm8 VEX.256 -mavx

_mm256_cmp_ps_mask __mmask8 _mm256_cmp_ps_mask(__m256 a, __m256 b, const int p)

VCMPPS k, ymm, ymm, imm8 EVEX.256 -mavx512vl

_mm256_mask_cmp_ps_mask __mmask8 _mm256_mask_cmp_ps_mask(__mmask8 m, __m256 a, __m256 b, const int p)

VCMPPS k, ymm, ymm, imm8 EVEX.256 -mavx512vl

_mm512_cmp_ps_mask __mmask16 _mm512_cmp_ps_mask(__m512 A, __m512 B, const int P)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmp_ps_mask __mmask16 _mm512_mask_cmp_ps_mask(__mmask16 U, __m512 A, __m512 B, const int P)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmp_round_ps_mask __mmask16 _mm512_cmp_round_ps_mask(__m512 A, __m512 B, const int P, const int R)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmp_round_ps_mask __mmask16 _mm512_mask_cmp_round_ps_mask(__mmask16 U, __m512 A, __m512 B, const int P, const int R)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpeq_ps_mask __mmask16 _mm512_cmpeq_ps_mask(__m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpeq_ps_mask __mmask16 _mm512_mask_cmpeq_ps_mask(__mmask16 k, __m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmple_ps_mask __mmask16 _mm512_cmple_ps_mask(__m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmple_ps_mask __mmask16 _mm512_mask_cmple_ps_mask(__mmask16 k, __m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmplt_ps_mask __mmask16 _mm512_cmplt_ps_mask(__m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmplt_ps_mask __mmask16 _mm512_mask_cmplt_ps_mask(__mmask16 k, __m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpneq_ps_mask __mmask16 _mm512_cmpneq_ps_mask(__m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpneq_ps_mask __mmask16 _mm512_mask_cmpneq_ps_mask(__mmask16 k, __m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpnle_ps_mask __mmask16 _mm512_cmpnle_ps_mask(__m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpnle_ps_mask __mmask16 _mm512_mask_cmpnle_ps_mask(__mmask16 k, __m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpnlt_ps_mask __mmask16 _mm512_cmpnlt_ps_mask(__m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpnlt_ps_mask __mmask16 _mm512_mask_cmpnlt_ps_mask(__mmask16 k, __m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpord_ps_mask __mmask16 _mm512_cmpord_ps_mask(__m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpord_ps_mask __mmask16 _mm512_mask_cmpord_ps_mask(__mmask16 k, __m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_cmpunord_ps_mask __mmask16 _mm512_cmpunord_ps_mask(__m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_cmpunord_ps_mask __mmask16 _mm512_mask_cmpunord_ps_mask(__mmask16 k, __m512 A, __m512 B)

VCMPPS k, zmm, zmm, imm8 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.