VCMPSD

VCMPSD is the VEX and EVEX form of CMPSD, whose page covers the scalar double compare and the string instruction that shares its name. It compares the low doubles of its two sources under the 32 predicates of VCMPPS, chosen by bits 4:0 of the immediate; the forms are those of VCMPSS. The VEX form, for AVX, writes all ones or zero to the low quadword of a separate destination, copies the high double from the first source and clears the bits above 127. The EVEX form, for AVX-512F or AVX10.1, writes bit 0 of a mask register, cleared when bit 0 of the write mask is, and takes {sae}.

Recorded on Zen 5#

• vcmpsd k5{k4}, xmm9, xmm9, {sae}, 0x1b, always false and signaling, met a quiet NaN with MXCSR.IM clear and raised nothing: no #XM and no flag.
• Without {sae}, vcmpsd k6{k4}, xmm14, qword ptr [mem], 0x1, less than, set IE for a signaling NaN and wrote 0.
• vcmpsd xmm1, xmm2, qword ptr [mem], 0x11, less than and quiet, compared 1.0 with a quiet NaN, wrote 0, left IE clear and kept the NaN in the high double from XMM2.

In compiled code#

In our builds at -O2, x >= 2.0 ? 1.0 : 0.0 shows the new predicates and the memory operand. With -march=x86-64-v3, GCC 14 compares straight with the constant in memory under predicate 9, not greater or equal, and selects with VBLENDVPD; Clang 23 keeps VCMPLESD with the operands swapped and a VANDPD. With -march=x86-64-v4 Clang writes vcmpgesd k1, xmm0, qword ptr [...], predicate 0Dh, and loads 1.0 with a zero-masked VMOVSD. Clang’s inline fmax likewise moves its cmpunordsd x, x test into K1 at -v4.

AMD’s latency spreadsheet for Zen 5 gives the VEX row 2 cycles on pipes FP2 and FP3, as for CMPSD, and the EVEX rows 3 cycles on FP1 and FP2, with a second macro-op for the memory form.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = xmm2.f64[0]
b = src3.f64[0]
xmm1.q[0] = -1 if fcmp(imm8, a, b) else 0
xmm1.q[1] = xmm2.q[1]
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# xmm1 is zeroed from bit 128 up

a = xmm2.f64[0]
b = src3.f64[0]
k1[0] = k2[0] and fcmp(imm8, a, b)
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# {sae}: no exception flags
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPD
• VADDPS
• VADDSD
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS

All 253 AVX instructions

More AVX10.1 instructions

• VANDNPS
• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSH
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD

All 686 AVX10.1 instructions