VCMPSH

VCMPSH compares the low halves of its two sources under one of the 32 predicates of VCMPPS, chosen by bits 4:0 of the immediate, and writes the result to bit 0 of a mask register, clearing the others; a write mask with bit 0 clear forces the result to 0. It is the scalar form of VCMPPH and, like the EVEX form of VCMPSS, has only a mask destination. The encoding is C2h with the F3 prefix in the 0F3A map; the second source is an xmm register or two bytes of memory, and {sae} keeps the compare from reporting invalid or denormal. VADDPH covers the format and the CPUID bits.

Selects and the comi intrinsics#

A mask bit feeds a masked move, so compilers use VCMPSH for a choice between two halves. At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 compiles x < y ? p : q on _Float16 values to vcmpltsh k1, xmm0, xmm1 and a merge-masked VMOVSH, and x == y ? p : q the same way with the equal predicate. GCC 14 uses VCMPSH for the first too, with the inverted predicate 5, not less than, so that the masked move picks q; for the equality it tests the flags of VUCOMISH and branches. Clang’s fminf16 on halves uses VCMPSH with the unordered predicate to catch a NaN first argument, as VMINSH’s page shows.

A plain x < y returned as an integer goes to the flags instead, as VCOMISH’s page shows. The intrinsics named after COMISH do not: _mm_comi_sh(x, y, _CMP_LT_OS) and _mm_cmp_sh_mask(x, y, _CMP_NEQ_UQ) both become VCMPSH into K0, with predicates 1 and 4, and a KMOV of the bit to a general-purpose register.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCMPSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = xmm2.f16[0]
b = src3.f16[0]
k1[0] = k2[0] and fcmp(imm8, a, b)
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# {sae}: no exception flags
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VANDPD
• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS

All 686 AVX10.1 instructions