Instruction
VCMPSH
Compares the low half-precision values with one of 32 predicates chosen by an immediate and writes the result to a mask register.
- Extensions
- Forms
- 2 (2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VCMPSH k {k}, xmm, xmm, imm8, {sae}
VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 | EVEX.LIG.F3.0F3A.W0 C2 /r ib | AVX10.1 or AVX512_FP16 |
VCMPSH k {k}, xmm, m16, imm8
VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 | EVEX.LIG.F3.0F3A.W0 C2 /r ib | AVX10.1 or AVX512_FP16 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VCMPSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cmp_round_sh_mask
__mmask8 _mm_cmp_round_sh_mask(__m128h X, __m128h Y, const int P, const int R) |
|
_mm_cmp_sh_mask
__mmask8 _mm_cmp_sh_mask(__m128h X, __m128h Y, const int P) |
|
_mm_comi_round_sh
int _mm_comi_round_sh(__m128h A, __m128h B, const int P, const int R) |
|
_mm_comi_sh
int _mm_comi_sh(__m128h A, __m128h B, const int pred) |
|
_mm_comieq_sh
int _mm_comieq_sh(__m128h __A, __m128h __B) |
|
_mm_comige_sh
int _mm_comige_sh(__m128h __A, __m128h __B) |
|
_mm_comigt_sh
int _mm_comigt_sh(__m128h __A, __m128h __B) |
|
_mm_comile_sh
int _mm_comile_sh(__m128h __A, __m128h __B) |
|
_mm_comilt_sh
int _mm_comilt_sh(__m128h __A, __m128h __B) |
|
_mm_comineq_sh
int _mm_comineq_sh(__m128h __A, __m128h __B) |
|
_mm_ucomieq_sh
int _mm_ucomieq_sh(__m128h __A, __m128h __B) |
|
_mm_ucomige_sh
int _mm_ucomige_sh(__m128h __A, __m128h __B) |
|
_mm_ucomigt_sh
int _mm_ucomigt_sh(__m128h __A, __m128h __B) |
|
_mm_ucomile_sh
int _mm_ucomile_sh(__m128h __A, __m128h __B) |
|
_mm_ucomilt_sh
int _mm_ucomilt_sh(__m128h __A, __m128h __B) |
|
_mm_ucomineq_sh
int _mm_ucomineq_sh(__m128h __A, __m128h __B) |
|
_mm_mask_cmp_round_sh_mask
__mmask8 _mm_mask_cmp_round_sh_mask(__mmask8 M, __m128h X, __m128h Y, const int P, const int R) |
|
_mm_mask_cmp_sh_mask
__mmask8 _mm_mask_cmp_sh_mask(__mmask8 M, __m128h X, __m128h Y, const int P) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP16_SCALAR | AVX10.1 or AVX512_FP16 | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VANDPD
- VANDPS
- VBLENDMPD
- VBLENDMPS
- VBROADCASTF32X2
- VBROADCASTF32X4
- VBROADCASTF32X8
- VBROADCASTF64X2
- VBROADCASTF64X4
- VBROADCASTI32X2
- VBROADCASTI32X4
- VBROADCASTI32X8
- VBROADCASTI64X2
- VBROADCASTI64X4
- VBROADCASTSD
- VBROADCASTSS
- VCMPPD
- VCMPPH
- VCMPPS
- VCMPSD
- VCMPSS
- VCOMISD
- VCOMISH
- VCOMISS
- VCOMPRESSPD
- VCOMPRESSPS
- VCVTDQ2PD
- VCVTDQ2PH
- VCVTDQ2PS
- VCVTNE2PS2BF16
- VCVTNEPS2BF16
- VCVTPD2DQ
- VCVTPD2PH
- VCVTPD2PS
- VCVTPD2QQ
- VCVTPD2UDQ
- VCVTPD2UQQ
- VCVTPH2DQ
- VCVTPH2PD
- VCVTPH2PS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.