VCMPSS

VCMPSS is the VEX and EVEX form of CMPSS, whose page covers the scalar compare and when compilers prefer it to the flags of COMISS. It compares the low singles of its two sources under the 32 predicates of VCMPPS, chosen by bits 4:0 of the immediate. The VEX form, for AVX, writes all ones or zero to the low single of a separate destination, copies singles 1 to 3 from the first source and clears the bits above 127. The EVEX form, for AVX-512F or AVX10.1, writes bit 0 of a mask register and clears the others; a write mask with bit 0 clear forces that bit to 0, and {sae} keeps the compare from reporting any exception.

Recorded on Zen 5#

• vcmpss xmm1, xmm2, xmm3, 0x4, not equal and quiet, compared a quiet NaN with a signaling one, wrote FFFFFFFFh and set MXCSR.IE: a quiet predicate does not cover a signaling NaN.
• vcmpss xmm0, xmm13, dword ptr [mem], 0xd, greater or equal, found the single nearest 1.0E-30 equal to itself and kept -1.0, the NaN and 1.0 of XMM13 above it.
• vcmpss k5{k6}, xmm0, xmm31, {sae}, 0x1c, with bit 0 of K6 clear, left K5 at 0 although the minimum normal single and 0.5 differ.

In compiled code#

In our builds at -O2 with -march=x86-64-v3, a < b ? c : d over float is VCMPSS and a VBLENDVPS in GCC 14 and Clang 23, GCC again computing not-less-than with c and d swapped. With -march=x86-64-v4 GCC keeps that, while Clang compares into K1 and selects with a masked VMOVSS. The VEX predicates include greater-than, 0Eh, yet _mm_cmpgt_ss still swaps its operands as on CMPSS’s page: GCC with VCMPLTPS and VMOVSS, Clang with VCMPLTSS and VBLENDPS.

AMD’s latency spreadsheet for Zen 5 gives the VEX row 2 cycles on pipes FP2 and FP3, as for CMPSS, and the EVEX rows, which write a mask register, 3 cycles on FP1 and FP2, with a second macro-op for the memory form. VCMPSD is the double form.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = xmm2.f32[0]
b = src3.f32[0]
xmm1.d[0] = -1 if fcmp(imm8, a, b) else 0
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# xmm1 is zeroed from bit 128 up

a = xmm2.f32[0]
b = src3.f32[0]
k1[0] = k2[0] and fcmp(imm8, a, b)
# imm8 & 31: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered ...
# {sae}: no exception flags
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCMPSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPD
• VADDPS
• VADDSD
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS

All 253 AVX instructions

More AVX10.1 instructions

• VANDPS
• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCOMISD
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX

All 686 AVX10.1 instructions