VCOMISBF16 instruction (AVX10.2)

VCOMISBF16 compares the low bfloat16 values of an XMM register and a register or 16 bits of memory and sets ZF, PF and CF as VCOMISS does: all three for unordered, CF alone for less, ZF alone for equal, none for greater, with OF, SF and AF cleared. It belongs to AVX10.2 and is the only scalar instruction among its bfloat16 arithmetic. The opcode is 2Fh in EVEX map 5 with the 66 prefix and W0, where VCOMISH has no prefix; EVEX.vvvv must be 1111b and the vector length is ignored.

One compare, not two

VCOMISS and VUCOMISS differ only in which NaNs raise the invalid-operation exception. VCOMISBF16 raises none, reads no MXCSR bit and reports a NaN of either kind as unordered, so the AVX10.2 specification (revision 7.0) defines no VUCOMISBF16; the entry’s exception class is E10NF. It reads denormals as zeros, as VADDBF16’s page explains, so 0001h and 0000h compare equal. Unlike VCOMXSS, it leaves OF and SF clear, so “less” needs JB or JA with the operands swapped, as for VCOMISS.

In our builds

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 uses VCOMISBF16 for the intrinsics only: _mm_comilt_sbh(a, b) swaps the operands and takes SETA, _mm_comige_sbh takes SETAE, _mm_comieq_sbh SETNP and SETE joined with AND, and _mm_comineq_sbh SETP and SETNE joined with OR. C’s compares on __bf16 values widen both to singles with a 16-bit shift instead: a < b and a <= b become VUCOMISS with SETA or SETAE, and a == b the AVX10.2 VUCOMXSS with SETE. Those keep denormals, so the C compare finds 0001h greater than 0000h. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Every encoding of VCOMISBF16 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCOMISBF16 xmm, xmm` VCOMISBF16_XMMbf16_XMMbf16_AVX512	`EVEX.LIG.66.MAP5.W0 2F /r`	AVX10.2
`VCOMISBF16 xmm, m16` VCOMISBF16_XMMbf16_MEMbf16_AVX512	`EVEX.LIG.66.MAP5.W0 2F /r`	AVX10.2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low bfloat16s of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from bfloat16 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = comi(xmm1.bf16[0], src2.bf16[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCOMISBF16 xmm, xmm/m16`
`xmm`	explicit	read
`xmm/m16`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E10NF

Attributes

What else XED records about the forms. How to read.

All forms: denormal inputs read as zero

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCOMISBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_comieq_sbh` `int _mm_comieq_sbh(__m128bh __A, __m128bh __B)`	`VCOMISBF16 xmm, xmm` EVEX.LIG -mavx10.2
`_mm_comige_sbh` `int _mm_comige_sbh(__m128bh __A, __m128bh __B)`	`VCOMISBF16 xmm, xmm` EVEX.LIG -mavx10.2
`_mm_comigt_sbh` `int _mm_comigt_sbh(__m128bh __A, __m128bh __B)`	`VCOMISBF16 xmm, xmm` EVEX.LIG -mavx10.2
`_mm_comile_sbh` `int _mm_comile_sbh(__m128bh __A, __m128bh __B)`	`VCOMISBF16 xmm, xmm` EVEX.LIG -mavx10.2
`_mm_comilt_sbh` `int _mm_comilt_sbh(__m128bh __A, __m128bh __B)`	`VCOMISBF16 xmm, xmm` EVEX.LIG -mavx10.2
`_mm_comineq_sbh` `int _mm_comineq_sbh(__m128bh __A, __m128bh __B)`	`VCOMISBF16 xmm, xmm` EVEX.LIG -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX10_2_BF16_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

One compare, not two#

In our builds#