x86-64.net

Instruction

VCOMISBF16

Compares the low bfloat16 values of two registers and sets ZF, PF and CF as COMISS does, without floating-point exceptions.

Extensions
Forms
2 (2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCOMISBF16 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCOMISBF16 xmm, xmm VCOMISBF16_XMMbf16_XMMbf16_AVX512EVEX.LIG.66.MAP5.W0 2F /rAVX10.2
VCOMISBF16 xmm, m16 VCOMISBF16_XMMbf16_MEMbf16_AVX512EVEX.LIG.66.MAP5.W0 2F /rAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCOMISBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_comieq_sbh int _mm_comieq_sbh(__m128bh __A, __m128bh __B)

VCOMISBF16 xmm, xmm EVEX.LIG -mavx10.2

_mm_comige_sbh int _mm_comige_sbh(__m128bh __A, __m128bh __B)

VCOMISBF16 xmm, xmm EVEX.LIG -mavx10.2

_mm_comigt_sbh int _mm_comigt_sbh(__m128bh __A, __m128bh __B)

VCOMISBF16 xmm, xmm EVEX.LIG -mavx10.2

_mm_comile_sbh int _mm_comile_sbh(__m128bh __A, __m128bh __B)

VCOMISBF16 xmm, xmm EVEX.LIG -mavx10.2

_mm_comilt_sbh int _mm_comilt_sbh(__m128bh __A, __m128bh __B)

VCOMISBF16 xmm, xmm EVEX.LIG -mavx10.2

_mm_comineq_sbh int _mm_comineq_sbh(__m128bh __A, __m128bh __B)

VCOMISBF16 xmm, xmm EVEX.LIG -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX10_2_BF16_SCALAR

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.