VCOMISD

VCOMISD is the VEX and EVEX form of COMISD: it compares the low doubles of a register and a register or eight bytes of memory, sets ZF, PF and CF, and raises the invalid-operation exception for any NaN, quiet ones included. COMISD’s page covers the flags and how compilers read them, and VCOMISS what the newer encodings add to a compare that writes no register: XMM16 to XMM31 and {sae} in the EVEX form, no write mask, and VEX.L ignored with a warning in Intel’s entry. The VEX form needs AVX, the EVEX form AVX512F or AVX10.1.

Recorded on Zen 5#

• vcomisd xmm1, qword ptr [mem] compared -1.0 with +infinity from memory under 7F80H and set CF alone: less, and no MXCSR flag, since an infinity is an ordinary operand here.
• {evex} vcomisd xmm0, qword ptr [mem] under FFC0H found the next double after 1.0 greater than 1.0, clearing ZF, PF and CF.
• {evex} vcomisd xmm5, xmm5, {sae}, a register against itself, gave equal, ZF alone.

In compiled code#

In our builds at -O2 with -march=x86-64-v3 or -v4, GCC 14 compiles a < b on doubles to vcomisd xmm1, xmm0 and SETA, the operands swapped as COMISD’s page shows, and Clang 23 to VUCOMISD. For _mm_comi_round_sd(a, b, _CMP_GT_OS, _MM_FROUND_NO_EXC), GCC emits vcomisd xmm0, xmm1, {sae} and SETA, with no swap for “greater”; a quiet predicate such as _CMP_LE_OQ gives VUCOMISD instead. Clang compiles both to VCMPSD into a mask register, vcmpgtsd k0, xmm0, xmm1, {sae} and vcmple_oqsd, read with KMOVW.

AMD’s latency spreadsheet for Zen 5 gives VCOMISD’s VEX and EVEX rows what it gives COMISD: two macro-ops, on pipes FP2/FP3 and FP4/FP5, two per cycle, with no latency listed.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = comi(xmm1.f64[0], src2.f64[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# a QNaN raises IE too
# {sae}: no exception flags

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCOMISD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VADDPS
• VADDSD
• VADDSS
• VADDSUBPD
• VADDSUBPS
• VANDNPD
• VANDNPS
• VANDPD
• VANDPS
• VBLENDPD
• VBLENDPS
• VBLENDVPD
• VBLENDVPS
• VBROADCASTF128
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD

All 253 AVX instructions

More AVX10.1 instructions

• VBLENDMPD
• VBLENDMPS
• VBROADCASTF32X2
• VBROADCASTF32X4
• VBROADCASTF32X8
• VBROADCASTF64X2
• VBROADCASTF64X4
• VBROADCASTI32X2
• VBROADCASTI32X4
• VBROADCASTI32X8
• VBROADCASTI64X2
• VBROADCASTI64X4
• VBROADCASTSD
• VBROADCASTSS
• VCMPPD
• VCMPPH
• VCMPPS
• VCMPSD
• VCMPSH
• VCMPSS
• VCOMISH
• VCOMISS
• VCOMPRESSPD
• VCOMPRESSPS
• VCVTDQ2PD
• VCVTDQ2PH
• VCVTDQ2PS
• VCVTNE2PS2BF16
• VCVTNEPS2BF16
• VCVTPD2DQ
• VCVTPD2PH
• VCVTPD2PS
• VCVTPD2QQ
• VCVTPD2UDQ
• VCVTPD2UQQ
• VCVTPH2DQ
• VCVTPH2PD
• VCVTPH2PS
• VCVTPH2PSX
• VCVTPH2QQ

All 686 AVX10.1 instructions